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Add scope trigger target and incr depth

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Aadi Desai 2023-05-12 14:04:42 +01:00
parent 0a06e93edf
commit 03219820e5
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1 changed files with 2 additions and 1 deletions
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make.py
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@ -241,6 +241,7 @@ class BaseSoC(SoCCore):
self.add_uartbone(name="debug_uart", baudrate=115200) self.add_uartbone(name="debug_uart", baudrate=115200)
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
analyzer_signals = [ analyzer_signals = [
self.audio.targ.re,
self.audio.targ.storage, self.audio.targ.storage,
self.audio.backpressure_48, self.audio.backpressure_48,
self.audio.leftrightaudio_48, self.audio.leftrightaudio_48,
@ -248,7 +249,7 @@ class BaseSoC(SoCCore):
] ]
self.submodules.analyzer = LiteScopeAnalyzer( self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, analyzer_signals,
depth = 1024, depth = 2048,
clock_domain = "sys", clock_domain = "sys",
samplerate = sys_clk_freq, samplerate = sys_clk_freq,
csr_csv = "analyzer.csv", csr_csv = "analyzer.csv",