From 03219820e51c43f2f22f9afecb726084cb1dda43 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Fri, 12 May 2023 14:04:42 +0100
Subject: [PATCH] Add scope trigger target and incr depth

---
 make.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/make.py b/make.py
index 4102f8e..271cedc 100755
--- a/make.py
+++ b/make.py
@@ -241,6 +241,7 @@ class BaseSoC(SoCCore):
         self.add_uartbone(name="debug_uart", baudrate=115200)
         from litescope import LiteScopeAnalyzer
         analyzer_signals = [
+            self.audio.targ.re,
             self.audio.targ.storage,
             self.audio.backpressure_48,
             self.audio.leftrightaudio_48,
@@ -248,7 +249,7 @@ class BaseSoC(SoCCore):
         ]
         self.submodules.analyzer = LiteScopeAnalyzer(
             analyzer_signals,
-            depth        = 1024,
+            depth        = 2048,
             clock_domain = "sys",
             samplerate   = sys_clk_freq,
             csr_csv      = "analyzer.csv",