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Add scope trigger target and incr depth
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parent
0a06e93edf
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3
make.py
3
make.py
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@ -241,6 +241,7 @@ class BaseSoC(SoCCore):
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self.add_uartbone(name="debug_uart", baudrate=115200)
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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self.audio.targ.re,
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self.audio.targ.storage,
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self.audio.backpressure_48,
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self.audio.leftrightaudio_48,
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@ -248,7 +249,7 @@ class BaseSoC(SoCCore):
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]
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self.submodules.analyzer = LiteScopeAnalyzer(
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analyzer_signals,
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depth = 1024,
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depth = 2048,
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clock_domain = "sys",
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samplerate = sys_clk_freq,
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csr_csv = "analyzer.csv",
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