supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-09-19 21:36:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add scope trigger target and incr depth

Browse source
This commit is contained in:
Aadi Desai 2023-05-12 14:04:42 +01:00
parent 0a06e93edf
commit 03219820e5
No known key found for this signature in database
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
make.py
View file

@ -241,6 +241,7 @@ class BaseSoC(SoCCore):
self.add_uartbone(name="debug_uart", baudrate=115200)
from litescope import LiteScopeAnalyzer
analyzer_signals = [
self.audio.targ.re,
self.audio.targ.storage,
self.audio.backpressure_48,
self.audio.leftrightaudio_48,
@ -248,7 +249,7 @@ class BaseSoC(SoCCore):
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth = 1024,
depth = 2048,
clock_domain = "sys",
samplerate = sys_clk_freq,
csr_csv = "analyzer.csv",