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16 lines
242 B
Systemverilog
16 lines
242 B
Systemverilog
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module flip
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( input var clk
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, output var ledr
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, output var ledg
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, output var ledb
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);
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logic [31:0] counter;
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always_ff @(posedge clk)
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counter <= counter + 1;
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assign {ledr, ledg, ledb} = ~counter[27:25];
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endmodule
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