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20 lines
2 KiB
Markdown
20 lines
2 KiB
Markdown
# Hi there 👋
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- 🔭 I’m currently working on building up this profile, my personal domain, and various subdomains
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- 🌱 I’m currently learning Python, and next Go
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- 💬 Ask me about anything, I like to learn and chat
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- 📫 How to reach me: [LinkedIn](https://www.linkedin.com/in/aadidesai/) / [Work Email](mailto:github@8bitsqu.id) / [Personal Email](mailto:aadi@8bitsqu.id)
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- 😄 Pronouns: he/him
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- ⚡ Fun fact: I'm basically flailing through life
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## Some of my projects
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I've linked a few repositories below that I've worked on. Over time I'll also be adding more personal projects to [my website](https://projects.8bitsqu.id/) as a way to practice writing / documenting my work.
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- [ARM-ish CPU Project, Imperial Y1 Summer Term](https://github.com/supleed2/ELEC40006-P1-CW/): General-purpose, ARM-based CPU designed in Quartus Prime Lite
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- [MIPS CPU Project, Imperial Y2 Winter Term](https://github.com/supleed2/ELEC50010-IAC-CW/): Working, synthesizable MIPS-compatible CPU, with memory-mapped I/O and peripherals, supporting the Intel Avalon memory interface
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- [Mars Rover Project, Imperial Y2 Summer Term](https://github.com/supleed2/ELEC50003-P1-CW/): Group project to design and build an autonomous rover including subsystems for motion, power management and control / communication
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- [Pet Tracker Project, Imperial Y3 Autumn Term](https://github.com/supleed2/ELEC60013-ES-CW1/): Pet Tracker using the FindMy Network as a backbone to provide basic data return from onboard sensors and ultra-low-power location tracking
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- [Synthesizer Project, Imperial Y3 Spring Term](https://github.com/supleed2/ELEC60013-ES-CW2/): Firmware for a single-octave synthesizer, written in C++, with multiple waveforms and more octaves usable by connecting multiple together
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- [SystemVerilog VSCode Language Client Extension](https://github.com/dalance/svls-vscode/): A VSCode extension designed to work with the [svls](https://github.com/dalance/svls/) language server and provide in-editor feedback, as well as snippets and syntax highlighting for SystemVerilog files
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