diff --git a/.gitignore b/.gitignore
index 1530978..4672533 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
-*.o
\ No newline at end of file
+*.o
+*.a
\ No newline at end of file
diff --git a/Makefile b/Makefile
index 4e13a65..18bd0ca 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@ SOURCE = Src/main.cpp tinyxml2/tinyxml2.cpp
INCLUDE = -I tinyxml2 -I cxxopts/include -I Src
OUT = svd2cpp
CC = g++
-FLAGS = -g -c -Wall
+FLAGS = -g -c -Wall -std=c++17
all: $(OBJS)
$(CC) -g $(OBJS) -o $(OUT) $(LFLAGS)
diff --git a/Sample/STM32F103xx.svd b/Sample/STM32F103xx.svd
new file mode 100644
index 0000000..3141910
--- /dev/null
+++ b/Sample/STM32F103xx.svd
@@ -0,0 +1,24923 @@
+
+
+ STM32F103xx
+ 1.3
+ STM32F103xx
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ FSMC
+ Flexible static memory controller
+ FSMC
+ 0xA0000000
+
+ 0x0
+ 0x1000
+ registers
+
+
+ FSMC
+ FSMC global interrupt
+ 48
+
+
+
+ BCR1
+ BCR1
+ SRAM/NOR-Flash chip-select control register
+ 1
+ 0x0
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR1
+ BTR1
+ SRAM/NOR-Flash chip-select timing register
+ 1
+ 0x4
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR2
+ BCR2
+ SRAM/NOR-Flash chip-select control register
+ 2
+ 0x8
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR2
+ BTR2
+ SRAM/NOR-Flash chip-select timing register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR3
+ BCR3
+ SRAM/NOR-Flash chip-select control register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR3
+ BTR3
+ SRAM/NOR-Flash chip-select timing register
+ 3
+ 0x14
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BCR4
+ BCR4
+ SRAM/NOR-Flash chip-select control register
+ 4
+ 0x18
+ 0x20
+ read-write
+ 0x000030D0
+
+
+ CBURSTRW
+ CBURSTRW
+ 19
+ 1
+
+
+ ASYNCWAIT
+ ASYNCWAIT
+ 15
+ 1
+
+
+ EXTMOD
+ EXTMOD
+ 14
+ 1
+
+
+ WAITEN
+ WAITEN
+ 13
+ 1
+
+
+ WREN
+ WREN
+ 12
+ 1
+
+
+ WAITCFG
+ WAITCFG
+ 11
+ 1
+
+
+ WRAPMOD
+ WRAPMOD
+ 10
+ 1
+
+
+ WAITPOL
+ WAITPOL
+ 9
+ 1
+
+
+ BURSTEN
+ BURSTEN
+ 8
+ 1
+
+
+ FACCEN
+ FACCEN
+ 6
+ 1
+
+
+ MWID
+ MWID
+ 4
+ 2
+
+
+ MTYP
+ MTYP
+ 2
+ 2
+
+
+ MUXEN
+ MUXEN
+ 1
+ 1
+
+
+ MBKEN
+ MBKEN
+ 0
+ 1
+
+
+
+
+ BTR4
+ BTR4
+ SRAM/NOR-Flash chip-select timing register
+ 4
+ 0x1C
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ BUSTURN
+ BUSTURN
+ 16
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ PCR2
+ PCR2
+ PC Card/NAND Flash control register
+ 2
+ 0x60
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR2
+ SR2
+ FIFO status and interrupt register
+ 2
+ 0x64
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM2
+ PMEM2
+ Common memory space timing register
+ 2
+ 0x68
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT2
+ PATT2
+ Attribute memory space timing register
+ 2
+ 0x6C
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ Attribute memory x databus HiZ
+ time
+ 24
+ 8
+
+
+ ATTHOLDx
+ Attribute memory x hold
+ time
+ 16
+ 8
+
+
+ ATTWAITx
+ Attribute memory x wait
+ time
+ 8
+ 8
+
+
+ ATTSETx
+ Attribute memory x setup
+ time
+ 0
+ 8
+
+
+
+
+ ECCR2
+ ECCR2
+ ECC result register 2
+ 0x74
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ECCx
+ ECC result
+ 0
+ 32
+
+
+
+
+ PCR3
+ PCR3
+ PC Card/NAND Flash control register
+ 3
+ 0x80
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR3
+ SR3
+ FIFO status and interrupt register
+ 3
+ 0x84
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM3
+ PMEM3
+ Common memory space timing register
+ 3
+ 0x88
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT3
+ PATT3
+ Attribute memory space timing register
+ 3
+ 0x8C
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ ATTHIZx
+ 24
+ 8
+
+
+ ATTHOLDx
+ ATTHOLDx
+ 16
+ 8
+
+
+ ATTWAITx
+ ATTWAITx
+ 8
+ 8
+
+
+ ATTSETx
+ ATTSETx
+ 0
+ 8
+
+
+
+
+ ECCR3
+ ECCR3
+ ECC result register 3
+ 0x94
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ECCx
+ ECCx
+ 0
+ 32
+
+
+
+
+ PCR4
+ PCR4
+ PC Card/NAND Flash control register
+ 4
+ 0xA0
+ 0x20
+ read-write
+ 0x00000018
+
+
+ ECCPS
+ ECCPS
+ 17
+ 3
+
+
+ TAR
+ TAR
+ 13
+ 4
+
+
+ TCLR
+ TCLR
+ 9
+ 4
+
+
+ ECCEN
+ ECCEN
+ 6
+ 1
+
+
+ PWID
+ PWID
+ 4
+ 2
+
+
+ PTYP
+ PTYP
+ 3
+ 1
+
+
+ PBKEN
+ PBKEN
+ 2
+ 1
+
+
+ PWAITEN
+ PWAITEN
+ 1
+ 1
+
+
+
+
+ SR4
+ SR4
+ FIFO status and interrupt register
+ 4
+ 0xA4
+ 0x20
+ 0x00000040
+
+
+ FEMPT
+ FEMPT
+ 6
+ 1
+ read-only
+
+
+ IFEN
+ IFEN
+ 5
+ 1
+ read-write
+
+
+ ILEN
+ ILEN
+ 4
+ 1
+ read-write
+
+
+ IREN
+ IREN
+ 3
+ 1
+ read-write
+
+
+ IFS
+ IFS
+ 2
+ 1
+ read-write
+
+
+ ILS
+ ILS
+ 1
+ 1
+ read-write
+
+
+ IRS
+ IRS
+ 0
+ 1
+ read-write
+
+
+
+
+ PMEM4
+ PMEM4
+ Common memory space timing register
+ 4
+ 0xA8
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ MEMHIZx
+ MEMHIZx
+ 24
+ 8
+
+
+ MEMHOLDx
+ MEMHOLDx
+ 16
+ 8
+
+
+ MEMWAITx
+ MEMWAITx
+ 8
+ 8
+
+
+ MEMSETx
+ MEMSETx
+ 0
+ 8
+
+
+
+
+ PATT4
+ PATT4
+ Attribute memory space timing register
+ 4
+ 0xAC
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ ATTHIZx
+ ATTHIZx
+ 24
+ 8
+
+
+ ATTHOLDx
+ ATTHOLDx
+ 16
+ 8
+
+
+ ATTWAITx
+ ATTWAITx
+ 8
+ 8
+
+
+ ATTSETx
+ ATTSETx
+ 0
+ 8
+
+
+
+
+ PIO4
+ PIO4
+ I/O space timing register 4
+ 0xB0
+ 0x20
+ read-write
+ 0xFCFCFCFC
+
+
+ IOHIZx
+ IOHIZx
+ 24
+ 8
+
+
+ IOHOLDx
+ IOHOLDx
+ 16
+ 8
+
+
+ IOWAITx
+ IOWAITx
+ 8
+ 8
+
+
+ IOSETx
+ IOSETx
+ 0
+ 8
+
+
+
+
+ BWTR1
+ BWTR1
+ SRAM/NOR-Flash write timing registers
+ 1
+ 0x104
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR2
+ BWTR2
+ SRAM/NOR-Flash write timing registers
+ 2
+ 0x10C
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR3
+ BWTR3
+ SRAM/NOR-Flash write timing registers
+ 3
+ 0x114
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+ BWTR4
+ BWTR4
+ SRAM/NOR-Flash write timing registers
+ 4
+ 0x11C
+ 0x20
+ read-write
+ 0x0FFFFFFF
+
+
+ ACCMOD
+ ACCMOD
+ 28
+ 2
+
+
+ DATLAT
+ DATLAT
+ 24
+ 4
+
+
+ CLKDIV
+ CLKDIV
+ 20
+ 4
+
+
+ DATAST
+ DATAST
+ 8
+ 8
+
+
+ ADDHLD
+ ADDHLD
+ 4
+ 4
+
+
+ ADDSET
+ ADDSET
+ 0
+ 4
+
+
+
+
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ PVD through EXTI line detection
+ interrupt
+ 1
+
+
+
+ CR
+ CR
+ Power control register
+ (PWR_CR)
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LPDS
+ Low Power Deep Sleep
+ 0
+ 1
+
+
+ PDDS
+ Power Down Deep Sleep
+ 1
+ 1
+
+
+ CWUF
+ Clear Wake-up Flag
+ 2
+ 1
+
+
+ CSBF
+ Clear STANDBY Flag
+ 3
+ 1
+
+
+ PVDE
+ Power Voltage Detector
+ Enable
+ 4
+ 1
+
+
+ PLS
+ PVD Level Selection
+ 5
+ 3
+
+
+ DBP
+ Disable Backup Domain write
+ protection
+ 8
+ 1
+
+
+
+
+ CSR
+ CSR
+ Power control register
+ (PWR_CR)
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ WUF
+ Wake-Up Flag
+ 0
+ 1
+ read-only
+
+
+ SBF
+ STANDBY Flag
+ 1
+ 1
+ read-only
+
+
+ PVDO
+ PVD Output
+ 2
+ 1
+ read-only
+
+
+ EWUP
+ Enable WKUP pin
+ 8
+ 1
+ read-write
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 5
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ HSION
+ Internal High Speed clock
+ enable
+ 0
+ 1
+ read-write
+
+
+ HSIRDY
+ Internal High Speed clock ready
+ flag
+ 1
+ 1
+ read-only
+
+
+ HSITRIM
+ Internal High Speed clock
+ trimming
+ 3
+ 5
+ read-write
+
+
+ HSICAL
+ Internal High Speed clock
+ Calibration
+ 8
+ 8
+ read-only
+
+
+ HSEON
+ External High Speed clock
+ enable
+ 16
+ 1
+ read-write
+
+
+ HSERDY
+ External High Speed clock ready
+ flag
+ 17
+ 1
+ read-only
+
+
+ HSEBYP
+ External High Speed clock
+ Bypass
+ 18
+ 1
+ read-write
+
+
+ CSSON
+ Clock Security System
+ enable
+ 19
+ 1
+ read-write
+
+
+ PLLON
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+ read-only
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ (RCC_CFGR)
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SW
+ System clock Switch
+ 0
+ 2
+ read-write
+
+
+ SWS
+ System Clock Switch Status
+ 2
+ 2
+ read-only
+
+
+ HPRE
+ AHB prescaler
+ 4
+ 4
+ read-write
+
+
+ PPRE1
+ APB Low speed prescaler
+ (APB1)
+ 8
+ 3
+ read-write
+
+
+ PPRE2
+ APB High speed prescaler
+ (APB2)
+ 11
+ 3
+ read-write
+
+
+ ADCPRE
+ ADC prescaler
+ 14
+ 2
+ read-write
+
+
+ PLLSRC
+ PLL entry clock source
+ 16
+ 1
+ read-write
+
+
+ PLLXTPRE
+ HSE divider for PLL entry
+ 17
+ 1
+ read-write
+
+
+ PLLMUL
+ PLL Multiplication Factor
+ 18
+ 4
+ read-write
+
+
+ OTGFSPRE
+ USB OTG FS prescaler
+ 22
+ 1
+ read-write
+
+
+ MCO
+ Microcontroller clock
+ output
+ 24
+ 3
+ read-write
+
+
+
+
+ CIR
+ CIR
+ Clock interrupt register
+ (RCC_CIR)
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LSIRDYF
+ LSI Ready Interrupt flag
+ 0
+ 1
+ read-only
+
+
+ LSERDYF
+ LSE Ready Interrupt flag
+ 1
+ 1
+ read-only
+
+
+ HSIRDYF
+ HSI Ready Interrupt flag
+ 2
+ 1
+ read-only
+
+
+ HSERDYF
+ HSE Ready Interrupt flag
+ 3
+ 1
+ read-only
+
+
+ PLLRDYF
+ PLL Ready Interrupt flag
+ 4
+ 1
+ read-only
+
+
+ CSSF
+ Clock Security System Interrupt
+ flag
+ 7
+ 1
+ read-only
+
+
+ LSIRDYIE
+ LSI Ready Interrupt Enable
+ 8
+ 1
+ read-write
+
+
+ LSERDYIE
+ LSE Ready Interrupt Enable
+ 9
+ 1
+ read-write
+
+
+ HSIRDYIE
+ HSI Ready Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ HSERDYIE
+ HSE Ready Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ PLLRDYIE
+ PLL Ready Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ LSIRDYC
+ LSI Ready Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ LSERDYC
+ LSE Ready Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ HSIRDYC
+ HSI Ready Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ HSERDYC
+ HSE Ready Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ PLLRDYC
+ PLL Ready Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ CSSC
+ Clock security system interrupt
+ clear
+ 23
+ 1
+ write-only
+
+
+
+
+ APB2RSTR
+ APB2RSTR
+ APB2 peripheral reset register
+ (RCC_APB2RSTR)
+ 0xC
+ 0x20
+ read-write
+ 0x000000000
+
+
+ AFIORST
+ Alternate function I/O
+ reset
+ 0
+ 1
+
+
+ IOPARST
+ IO port A reset
+ 2
+ 1
+
+
+ IOPBRST
+ IO port B reset
+ 3
+ 1
+
+
+ IOPCRST
+ IO port C reset
+ 4
+ 1
+
+
+ IOPDRST
+ IO port D reset
+ 5
+ 1
+
+
+ IOPERST
+ IO port E reset
+ 6
+ 1
+
+
+ IOPFRST
+ IO port F reset
+ 7
+ 1
+
+
+ IOPGRST
+ IO port G reset
+ 8
+ 1
+
+
+ ADC1RST
+ ADC 1 interface reset
+ 9
+ 1
+
+
+ ADC2RST
+ ADC 2 interface reset
+ 10
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ TIM8RST
+ TIM8 timer reset
+ 13
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ ADC3RST
+ ADC 3 interface reset
+ 15
+ 1
+
+
+ TIM9RST
+ TIM9 timer reset
+ 19
+ 1
+
+
+ TIM10RST
+ TIM10 timer reset
+ 20
+ 1
+
+
+ TIM11RST
+ TIM11 timer reset
+ 21
+ 1
+
+
+
+
+ APB1RSTR
+ APB1RSTR
+ APB1 peripheral reset register
+ (RCC_APB1RSTR)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM4RST
+ Timer 4 reset
+ 2
+ 1
+
+
+ TIM5RST
+ Timer 5 reset
+ 3
+ 1
+
+
+ TIM6RST
+ Timer 6 reset
+ 4
+ 1
+
+
+ TIM7RST
+ Timer 7 reset
+ 5
+ 1
+
+
+ TIM12RST
+ Timer 12 reset
+ 6
+ 1
+
+
+ TIM13RST
+ Timer 13 reset
+ 7
+ 1
+
+
+ TIM14RST
+ Timer 14 reset
+ 8
+ 1
+
+
+ WWDGRST
+ Window watchdog reset
+ 11
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ SPI3RST
+ SPI3 reset
+ 15
+ 1
+
+
+ USART2RST
+ USART 2 reset
+ 17
+ 1
+
+
+ USART3RST
+ USART 3 reset
+ 18
+ 1
+
+
+ UART4RST
+ UART 4 reset
+ 19
+ 1
+
+
+ UART5RST
+ UART 5 reset
+ 20
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ USBRST
+ USB reset
+ 23
+ 1
+
+
+ CANRST
+ CAN reset
+ 25
+ 1
+
+
+ BKPRST
+ Backup interface reset
+ 27
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+ DACRST
+ DAC interface reset
+ 29
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB Peripheral Clock enable register
+ (RCC_AHBENR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ DMA1EN
+ DMA1 clock enable
+ 0
+ 1
+
+
+ DMA2EN
+ DMA2 clock enable
+ 1
+ 1
+
+
+ SRAMEN
+ SRAM interface clock
+ enable
+ 2
+ 1
+
+
+ FLITFEN
+ FLITF clock enable
+ 4
+ 1
+
+
+ CRCEN
+ CRC clock enable
+ 6
+ 1
+
+
+ FSMCEN
+ FSMC clock enable
+ 8
+ 1
+
+
+ SDIOEN
+ SDIO clock enable
+ 10
+ 1
+
+
+
+
+ APB2ENR
+ APB2ENR
+ APB2 peripheral clock enable register
+ (RCC_APB2ENR)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFIOEN
+ Alternate function I/O clock
+ enable
+ 0
+ 1
+
+
+ IOPAEN
+ I/O port A clock enable
+ 2
+ 1
+
+
+ IOPBEN
+ I/O port B clock enable
+ 3
+ 1
+
+
+ IOPCEN
+ I/O port C clock enable
+ 4
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ 5
+ 1
+
+
+ IOPEEN
+ I/O port E clock enable
+ 6
+ 1
+
+
+ IOPFEN
+ I/O port F clock enable
+ 7
+ 1
+
+
+ IOPGEN
+ I/O port G clock enable
+ 8
+ 1
+
+
+ ADC1EN
+ ADC 1 interface clock
+ enable
+ 9
+ 1
+
+
+ ADC2EN
+ ADC 2 interface clock
+ enable
+ 10
+ 1
+
+
+ TIM1EN
+ TIM1 Timer clock enable
+ 11
+ 1
+
+
+ SPI1EN
+ SPI 1 clock enable
+ 12
+ 1
+
+
+ TIM8EN
+ TIM8 Timer clock enable
+ 13
+ 1
+
+
+ USART1EN
+ USART1 clock enable
+ 14
+ 1
+
+
+ ADC3EN
+ ADC3 interface clock
+ enable
+ 15
+ 1
+
+
+ TIM9EN
+ TIM9 Timer clock enable
+ 19
+ 1
+
+
+ TIM10EN
+ TIM10 Timer clock enable
+ 20
+ 1
+
+
+ TIM11EN
+ TIM11 Timer clock enable
+ 21
+ 1
+
+
+
+
+ APB1ENR
+ APB1ENR
+ APB1 peripheral clock enable register
+ (RCC_APB1ENR)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2EN
+ Timer 2 clock enable
+ 0
+ 1
+
+
+ TIM3EN
+ Timer 3 clock enable
+ 1
+ 1
+
+
+ TIM4EN
+ Timer 4 clock enable
+ 2
+ 1
+
+
+ TIM5EN
+ Timer 5 clock enable
+ 3
+ 1
+
+
+ TIM6EN
+ Timer 6 clock enable
+ 4
+ 1
+
+
+ TIM7EN
+ Timer 7 clock enable
+ 5
+ 1
+
+
+ TIM12EN
+ Timer 12 clock enable
+ 6
+ 1
+
+
+ TIM13EN
+ Timer 13 clock enable
+ 7
+ 1
+
+
+ TIM14EN
+ Timer 14 clock enable
+ 8
+ 1
+
+
+ WWDGEN
+ Window watchdog clock
+ enable
+ 11
+ 1
+
+
+ SPI2EN
+ SPI 2 clock enable
+ 14
+ 1
+
+
+ SPI3EN
+ SPI 3 clock enable
+ 15
+ 1
+
+
+ USART2EN
+ USART 2 clock enable
+ 17
+ 1
+
+
+ USART3EN
+ USART 3 clock enable
+ 18
+ 1
+
+
+ UART4EN
+ UART 4 clock enable
+ 19
+ 1
+
+
+ UART5EN
+ UART 5 clock enable
+ 20
+ 1
+
+
+ I2C1EN
+ I2C 1 clock enable
+ 21
+ 1
+
+
+ I2C2EN
+ I2C 2 clock enable
+ 22
+ 1
+
+
+ USBEN
+ USB clock enable
+ 23
+ 1
+
+
+ CANEN
+ CAN clock enable
+ 25
+ 1
+
+
+ BKPEN
+ Backup interface clock
+ enable
+ 27
+ 1
+
+
+ PWREN
+ Power interface clock
+ enable
+ 28
+ 1
+
+
+ DACEN
+ DAC interface clock enable
+ 29
+ 1
+
+
+
+
+ BDCR
+ BDCR
+ Backup domain control register
+ (RCC_BDCR)
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ LSEON
+ External Low Speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+ LSERDY
+ External Low Speed oscillator
+ ready
+ 1
+ 1
+ read-only
+
+
+ LSEBYP
+ External Low Speed oscillator
+ bypass
+ 2
+ 1
+ read-write
+
+
+ RTCSEL
+ RTC clock source selection
+ 8
+ 2
+ read-write
+
+
+ RTCEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ BDRST
+ Backup domain software
+ reset
+ 16
+ 1
+ read-write
+
+
+
+
+ CSR
+ CSR
+ Control/status register
+ (RCC_CSR)
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LSION
+ Internal low speed oscillator
+ enable
+ 0
+ 1
+ read-write
+
+
+ LSIRDY
+ Internal low speed oscillator
+ ready
+ 1
+ 1
+ read-only
+
+
+ RMVF
+ Remove reset flag
+ 24
+ 1
+ read-write
+
+
+ PINRSTF
+ PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ IWDGRSTF
+ Independent watchdog reset
+ flag
+ 29
+ 1
+ read-write
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+ read-write
+
+
+ LPWRRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+
+
+
+
+ GPIOA
+ General purpose I/O
+ GPIO
+ 0x40010800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CRL
+ CRL
+ Port configuration register low
+ (GPIOn_CRL)
+ 0x0
+ 0x20
+ read-write
+ 0x44444444
+
+
+ MODE0
+ Port n.0 mode bits
+ 0
+ 2
+
+
+ CNF0
+ Port n.0 configuration
+ bits
+ 2
+ 2
+
+
+ MODE1
+ Port n.1 mode bits
+ 4
+ 2
+
+
+ CNF1
+ Port n.1 configuration
+ bits
+ 6
+ 2
+
+
+ MODE2
+ Port n.2 mode bits
+ 8
+ 2
+
+
+ CNF2
+ Port n.2 configuration
+ bits
+ 10
+ 2
+
+
+ MODE3
+ Port n.3 mode bits
+ 12
+ 2
+
+
+ CNF3
+ Port n.3 configuration
+ bits
+ 14
+ 2
+
+
+ MODE4
+ Port n.4 mode bits
+ 16
+ 2
+
+
+ CNF4
+ Port n.4 configuration
+ bits
+ 18
+ 2
+
+
+ MODE5
+ Port n.5 mode bits
+ 20
+ 2
+
+
+ CNF5
+ Port n.5 configuration
+ bits
+ 22
+ 2
+
+
+ MODE6
+ Port n.6 mode bits
+ 24
+ 2
+
+
+ CNF6
+ Port n.6 configuration
+ bits
+ 26
+ 2
+
+
+ MODE7
+ Port n.7 mode bits
+ 28
+ 2
+
+
+ CNF7
+ Port n.7 configuration
+ bits
+ 30
+ 2
+
+
+
+
+ CRH
+ CRH
+ Port configuration register high
+ (GPIOn_CRL)
+ 0x4
+ 0x20
+ read-write
+ 0x44444444
+
+
+ MODE8
+ Port n.8 mode bits
+ 0
+ 2
+
+
+ CNF8
+ Port n.8 configuration
+ bits
+ 2
+ 2
+
+
+ MODE9
+ Port n.9 mode bits
+ 4
+ 2
+
+
+ CNF9
+ Port n.9 configuration
+ bits
+ 6
+ 2
+
+
+ MODE10
+ Port n.10 mode bits
+ 8
+ 2
+
+
+ CNF10
+ Port n.10 configuration
+ bits
+ 10
+ 2
+
+
+ MODE11
+ Port n.11 mode bits
+ 12
+ 2
+
+
+ CNF11
+ Port n.11 configuration
+ bits
+ 14
+ 2
+
+
+ MODE12
+ Port n.12 mode bits
+ 16
+ 2
+
+
+ CNF12
+ Port n.12 configuration
+ bits
+ 18
+ 2
+
+
+ MODE13
+ Port n.13 mode bits
+ 20
+ 2
+
+
+ CNF13
+ Port n.13 configuration
+ bits
+ 22
+ 2
+
+
+ MODE14
+ Port n.14 mode bits
+ 24
+ 2
+
+
+ CNF14
+ Port n.14 configuration
+ bits
+ 26
+ 2
+
+
+ MODE15
+ Port n.15 mode bits
+ 28
+ 2
+
+
+ CNF15
+ Port n.15 configuration
+ bits
+ 30
+ 2
+
+
+
+
+ IDR
+ IDR
+ Port input data register
+ (GPIOn_IDR)
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDR0
+ Port input data
+ 0
+ 1
+
+
+ IDR1
+ Port input data
+ 1
+ 1
+
+
+ IDR2
+ Port input data
+ 2
+ 1
+
+
+ IDR3
+ Port input data
+ 3
+ 1
+
+
+ IDR4
+ Port input data
+ 4
+ 1
+
+
+ IDR5
+ Port input data
+ 5
+ 1
+
+
+ IDR6
+ Port input data
+ 6
+ 1
+
+
+ IDR7
+ Port input data
+ 7
+ 1
+
+
+ IDR8
+ Port input data
+ 8
+ 1
+
+
+ IDR9
+ Port input data
+ 9
+ 1
+
+
+ IDR10
+ Port input data
+ 10
+ 1
+
+
+ IDR11
+ Port input data
+ 11
+ 1
+
+
+ IDR12
+ Port input data
+ 12
+ 1
+
+
+ IDR13
+ Port input data
+ 13
+ 1
+
+
+ IDR14
+ Port input data
+ 14
+ 1
+
+
+ IDR15
+ Port input data
+ 15
+ 1
+
+
+
+
+ ODR
+ ODR
+ Port output data register
+ (GPIOn_ODR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODR0
+ Port output data
+ 0
+ 1
+
+
+ ODR1
+ Port output data
+ 1
+ 1
+
+
+ ODR2
+ Port output data
+ 2
+ 1
+
+
+ ODR3
+ Port output data
+ 3
+ 1
+
+
+ ODR4
+ Port output data
+ 4
+ 1
+
+
+ ODR5
+ Port output data
+ 5
+ 1
+
+
+ ODR6
+ Port output data
+ 6
+ 1
+
+
+ ODR7
+ Port output data
+ 7
+ 1
+
+
+ ODR8
+ Port output data
+ 8
+ 1
+
+
+ ODR9
+ Port output data
+ 9
+ 1
+
+
+ ODR10
+ Port output data
+ 10
+ 1
+
+
+ ODR11
+ Port output data
+ 11
+ 1
+
+
+ ODR12
+ Port output data
+ 12
+ 1
+
+
+ ODR13
+ Port output data
+ 13
+ 1
+
+
+ ODR14
+ Port output data
+ 14
+ 1
+
+
+ ODR15
+ Port output data
+ 15
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ Port bit set/reset register
+ (GPIOn_BSRR)
+ 0x10
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BS0
+ Set bit 0
+ 0
+ 1
+
+
+ BS1
+ Set bit 1
+ 1
+ 1
+
+
+ BS2
+ Set bit 1
+ 2
+ 1
+
+
+ BS3
+ Set bit 3
+ 3
+ 1
+
+
+ BS4
+ Set bit 4
+ 4
+ 1
+
+
+ BS5
+ Set bit 5
+ 5
+ 1
+
+
+ BS6
+ Set bit 6
+ 6
+ 1
+
+
+ BS7
+ Set bit 7
+ 7
+ 1
+
+
+ BS8
+ Set bit 8
+ 8
+ 1
+
+
+ BS9
+ Set bit 9
+ 9
+ 1
+
+
+ BS10
+ Set bit 10
+ 10
+ 1
+
+
+ BS11
+ Set bit 11
+ 11
+ 1
+
+
+ BS12
+ Set bit 12
+ 12
+ 1
+
+
+ BS13
+ Set bit 13
+ 13
+ 1
+
+
+ BS14
+ Set bit 14
+ 14
+ 1
+
+
+ BS15
+ Set bit 15
+ 15
+ 1
+
+
+ BR0
+ Reset bit 0
+ 16
+ 1
+
+
+ BR1
+ Reset bit 1
+ 17
+ 1
+
+
+ BR2
+ Reset bit 2
+ 18
+ 1
+
+
+ BR3
+ Reset bit 3
+ 19
+ 1
+
+
+ BR4
+ Reset bit 4
+ 20
+ 1
+
+
+ BR5
+ Reset bit 5
+ 21
+ 1
+
+
+ BR6
+ Reset bit 6
+ 22
+ 1
+
+
+ BR7
+ Reset bit 7
+ 23
+ 1
+
+
+ BR8
+ Reset bit 8
+ 24
+ 1
+
+
+ BR9
+ Reset bit 9
+ 25
+ 1
+
+
+ BR10
+ Reset bit 10
+ 26
+ 1
+
+
+ BR11
+ Reset bit 11
+ 27
+ 1
+
+
+ BR12
+ Reset bit 12
+ 28
+ 1
+
+
+ BR13
+ Reset bit 13
+ 29
+ 1
+
+
+ BR14
+ Reset bit 14
+ 30
+ 1
+
+
+ BR15
+ Reset bit 15
+ 31
+ 1
+
+
+
+
+ BRR
+ BRR
+ Port bit reset register
+ (GPIOn_BRR)
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR0
+ Reset bit 0
+ 0
+ 1
+
+
+ BR1
+ Reset bit 1
+ 1
+ 1
+
+
+ BR2
+ Reset bit 1
+ 2
+ 1
+
+
+ BR3
+ Reset bit 3
+ 3
+ 1
+
+
+ BR4
+ Reset bit 4
+ 4
+ 1
+
+
+ BR5
+ Reset bit 5
+ 5
+ 1
+
+
+ BR6
+ Reset bit 6
+ 6
+ 1
+
+
+ BR7
+ Reset bit 7
+ 7
+ 1
+
+
+ BR8
+ Reset bit 8
+ 8
+ 1
+
+
+ BR9
+ Reset bit 9
+ 9
+ 1
+
+
+ BR10
+ Reset bit 10
+ 10
+ 1
+
+
+ BR11
+ Reset bit 11
+ 11
+ 1
+
+
+ BR12
+ Reset bit 12
+ 12
+ 1
+
+
+ BR13
+ Reset bit 13
+ 13
+ 1
+
+
+ BR14
+ Reset bit 14
+ 14
+ 1
+
+
+ BR15
+ Reset bit 15
+ 15
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ Port configuration lock
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCK0
+ Port A Lock bit 0
+ 0
+ 1
+
+
+ LCK1
+ Port A Lock bit 1
+ 1
+ 1
+
+
+ LCK2
+ Port A Lock bit 2
+ 2
+ 1
+
+
+ LCK3
+ Port A Lock bit 3
+ 3
+ 1
+
+
+ LCK4
+ Port A Lock bit 4
+ 4
+ 1
+
+
+ LCK5
+ Port A Lock bit 5
+ 5
+ 1
+
+
+ LCK6
+ Port A Lock bit 6
+ 6
+ 1
+
+
+ LCK7
+ Port A Lock bit 7
+ 7
+ 1
+
+
+ LCK8
+ Port A Lock bit 8
+ 8
+ 1
+
+
+ LCK9
+ Port A Lock bit 9
+ 9
+ 1
+
+
+ LCK10
+ Port A Lock bit 10
+ 10
+ 1
+
+
+ LCK11
+ Port A Lock bit 11
+ 11
+ 1
+
+
+ LCK12
+ Port A Lock bit 12
+ 12
+ 1
+
+
+ LCK13
+ Port A Lock bit 13
+ 13
+ 1
+
+
+ LCK14
+ Port A Lock bit 14
+ 14
+ 1
+
+
+ LCK15
+ Port A Lock bit 15
+ 15
+ 1
+
+
+ LCKK
+ Lock key
+ 16
+ 1
+
+
+
+
+
+
+ GPIOB
+ 0x40010C00
+
+
+ GPIOC
+ 0x40011000
+
+
+ GPIOD
+ 0x40011400
+
+
+ GPIOE
+ 0x40011800
+
+
+ GPIOF
+ 0x40011C00
+
+
+ GPIOG
+ 0x40012000
+
+
+ AFIO
+ Alternate function I/O
+ AFIO
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ EVCR
+ EVCR
+ Event Control Register
+ (AFIO_EVCR)
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PIN
+ Pin selection
+ 0
+ 4
+
+
+ PORT
+ Port selection
+ 4
+ 3
+
+
+ EVOE
+ Event Output Enable
+ 7
+ 1
+
+
+
+
+ MAPR
+ MAPR
+ AF remap and debug I/O configuration
+ register (AFIO_MAPR)
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SPI1_REMAP
+ SPI1 remapping
+ 0
+ 1
+ read-write
+
+
+ I2C1_REMAP
+ I2C1 remapping
+ 1
+ 1
+ read-write
+
+
+ USART1_REMAP
+ USART1 remapping
+ 2
+ 1
+ read-write
+
+
+ USART2_REMAP
+ USART2 remapping
+ 3
+ 1
+ read-write
+
+
+ USART3_REMAP
+ USART3 remapping
+ 4
+ 2
+ read-write
+
+
+ TIM1_REMAP
+ TIM1 remapping
+ 6
+ 2
+ read-write
+
+
+ TIM2_REMAP
+ TIM2 remapping
+ 8
+ 2
+ read-write
+
+
+ TIM3_REMAP
+ TIM3 remapping
+ 10
+ 2
+ read-write
+
+
+ TIM4_REMAP
+ TIM4 remapping
+ 12
+ 1
+ read-write
+
+
+ CAN_REMAP
+ CAN1 remapping
+ 13
+ 2
+ read-write
+
+
+ PD01_REMAP
+ Port D0/Port D1 mapping on
+ OSCIN/OSCOUT
+ 15
+ 1
+ read-write
+
+
+ TIM5CH4_IREMAP
+ Set and cleared by
+ software
+ 16
+ 1
+ read-write
+
+
+ ADC1_ETRGINJ_REMAP
+ ADC 1 External trigger injected
+ conversion remapping
+ 17
+ 1
+ read-write
+
+
+ ADC1_ETRGREG_REMAP
+ ADC 1 external trigger regular
+ conversion remapping
+ 18
+ 1
+ read-write
+
+
+ ADC2_ETRGINJ_REMAP
+ ADC 2 external trigger injected
+ conversion remapping
+ 19
+ 1
+ read-write
+
+
+ ADC2_ETRGREG_REMAP
+ ADC 2 external trigger regular
+ conversion remapping
+ 20
+ 1
+ read-write
+
+
+ SWJ_CFG
+ Serial wire JTAG
+ configuration
+ 24
+ 3
+ write-only
+
+
+
+
+ EXTICR1
+ EXTICR1
+ External interrupt configuration register 1
+ (AFIO_EXTICR1)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI0
+ EXTI0 configuration
+ 0
+ 4
+
+
+ EXTI1
+ EXTI1 configuration
+ 4
+ 4
+
+
+ EXTI2
+ EXTI2 configuration
+ 8
+ 4
+
+
+ EXTI3
+ EXTI3 configuration
+ 12
+ 4
+
+
+
+
+ EXTICR2
+ EXTICR2
+ External interrupt configuration register 2
+ (AFIO_EXTICR2)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI4
+ EXTI4 configuration
+ 0
+ 4
+
+
+ EXTI5
+ EXTI5 configuration
+ 4
+ 4
+
+
+ EXTI6
+ EXTI6 configuration
+ 8
+ 4
+
+
+ EXTI7
+ EXTI7 configuration
+ 12
+ 4
+
+
+
+
+ EXTICR3
+ EXTICR3
+ External interrupt configuration register 3
+ (AFIO_EXTICR3)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI8
+ EXTI8 configuration
+ 0
+ 4
+
+
+ EXTI9
+ EXTI9 configuration
+ 4
+ 4
+
+
+ EXTI10
+ EXTI10 configuration
+ 8
+ 4
+
+
+ EXTI11
+ EXTI11 configuration
+ 12
+ 4
+
+
+
+
+ EXTICR4
+ EXTICR4
+ External interrupt configuration register 4
+ (AFIO_EXTICR4)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI12
+ EXTI12 configuration
+ 0
+ 4
+
+
+ EXTI13
+ EXTI13 configuration
+ 4
+ 4
+
+
+ EXTI14
+ EXTI14 configuration
+ 8
+ 4
+
+
+ EXTI15
+ EXTI15 configuration
+ 12
+ 4
+
+
+
+
+ MAPR2
+ MAPR2
+ AF remap and debug I/O configuration
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM9_REMAP
+ TIM9 remapping
+ 5
+ 1
+
+
+ TIM10_REMAP
+ TIM10 remapping
+ 6
+ 1
+
+
+ TIM11_REMAP
+ TIM11 remapping
+ 7
+ 1
+
+
+ TIM13_REMAP
+ TIM13 remapping
+ 8
+ 1
+
+
+ TIM14_REMAP
+ TIM14 remapping
+ 9
+ 1
+
+
+ FSMC_NADV
+ NADV connect/disconnect
+ 10
+ 1
+
+
+
+
+
+
+ EXTI
+ EXTI
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TAMPER
+ Tamper interrupt
+ 2
+
+
+ EXTI0
+ EXTI Line0 interrupt
+ 6
+
+
+ EXTI1
+ EXTI Line1 interrupt
+ 7
+
+
+ EXTI2
+ EXTI Line2 interrupt
+ 8
+
+
+ EXTI3
+ EXTI Line3 interrupt
+ 9
+
+
+ EXTI4
+ EXTI Line4 interrupt
+ 10
+
+
+ EXTI9_5
+ EXTI Line[9:5] interrupts
+ 23
+
+
+ EXTI15_10
+ EXTI Line[15:10] interrupts
+ 40
+
+
+
+ IMR
+ IMR
+ Interrupt mask register
+ (EXTI_IMR)
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MR0
+ Interrupt Mask on line 0
+ 0
+ 1
+
+
+ MR1
+ Interrupt Mask on line 1
+ 1
+ 1
+
+
+ MR2
+ Interrupt Mask on line 2
+ 2
+ 1
+
+
+ MR3
+ Interrupt Mask on line 3
+ 3
+ 1
+
+
+ MR4
+ Interrupt Mask on line 4
+ 4
+ 1
+
+
+ MR5
+ Interrupt Mask on line 5
+ 5
+ 1
+
+
+ MR6
+ Interrupt Mask on line 6
+ 6
+ 1
+
+
+ MR7
+ Interrupt Mask on line 7
+ 7
+ 1
+
+
+ MR8
+ Interrupt Mask on line 8
+ 8
+ 1
+
+
+ MR9
+ Interrupt Mask on line 9
+ 9
+ 1
+
+
+ MR10
+ Interrupt Mask on line 10
+ 10
+ 1
+
+
+ MR11
+ Interrupt Mask on line 11
+ 11
+ 1
+
+
+ MR12
+ Interrupt Mask on line 12
+ 12
+ 1
+
+
+ MR13
+ Interrupt Mask on line 13
+ 13
+ 1
+
+
+ MR14
+ Interrupt Mask on line 14
+ 14
+ 1
+
+
+ MR15
+ Interrupt Mask on line 15
+ 15
+ 1
+
+
+ MR16
+ Interrupt Mask on line 16
+ 16
+ 1
+
+
+ MR17
+ Interrupt Mask on line 17
+ 17
+ 1
+
+
+ MR18
+ Interrupt Mask on line 18
+ 18
+ 1
+
+
+
+
+ EMR
+ EMR
+ Event mask register (EXTI_EMR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MR0
+ Event Mask on line 0
+ 0
+ 1
+
+
+ MR1
+ Event Mask on line 1
+ 1
+ 1
+
+
+ MR2
+ Event Mask on line 2
+ 2
+ 1
+
+
+ MR3
+ Event Mask on line 3
+ 3
+ 1
+
+
+ MR4
+ Event Mask on line 4
+ 4
+ 1
+
+
+ MR5
+ Event Mask on line 5
+ 5
+ 1
+
+
+ MR6
+ Event Mask on line 6
+ 6
+ 1
+
+
+ MR7
+ Event Mask on line 7
+ 7
+ 1
+
+
+ MR8
+ Event Mask on line 8
+ 8
+ 1
+
+
+ MR9
+ Event Mask on line 9
+ 9
+ 1
+
+
+ MR10
+ Event Mask on line 10
+ 10
+ 1
+
+
+ MR11
+ Event Mask on line 11
+ 11
+ 1
+
+
+ MR12
+ Event Mask on line 12
+ 12
+ 1
+
+
+ MR13
+ Event Mask on line 13
+ 13
+ 1
+
+
+ MR14
+ Event Mask on line 14
+ 14
+ 1
+
+
+ MR15
+ Event Mask on line 15
+ 15
+ 1
+
+
+ MR16
+ Event Mask on line 16
+ 16
+ 1
+
+
+ MR17
+ Event Mask on line 17
+ 17
+ 1
+
+
+ MR18
+ Event Mask on line 18
+ 18
+ 1
+
+
+
+
+ RTSR
+ RTSR
+ Rising Trigger selection register
+ (EXTI_RTSR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ TR1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ TR2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ TR3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ TR4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ TR5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ TR6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ TR7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ TR8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ TR9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ TR10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ TR11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ TR12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ TR13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ TR14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ TR15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ TR16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ TR17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ TR18
+ Rising trigger event configuration of
+ line 18
+ 18
+ 1
+
+
+
+
+ FTSR
+ FTSR
+ Falling Trigger selection register
+ (EXTI_FTSR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ TR1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ TR2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ TR3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ TR4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ TR5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ TR6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ TR7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ TR8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ TR9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ TR10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ TR11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ TR12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ TR13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ TR14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ TR15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ TR16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ TR17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ TR18
+ Falling trigger event configuration of
+ line 18
+ 18
+ 1
+
+
+
+
+ SWIER
+ SWIER
+ Software interrupt event register
+ (EXTI_SWIER)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIER0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWIER1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWIER2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWIER3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWIER4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWIER5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWIER6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWIER7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWIER8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWIER9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWIER10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWIER11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWIER12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWIER13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWIER14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWIER15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWIER16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWIER17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWIER18
+ Software Interrupt on line
+ 18
+ 18
+ 1
+
+
+
+
+ PR
+ PR
+ Pending register (EXTI_PR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR0
+ Pending bit 0
+ 0
+ 1
+
+
+ PR1
+ Pending bit 1
+ 1
+ 1
+
+
+ PR2
+ Pending bit 2
+ 2
+ 1
+
+
+ PR3
+ Pending bit 3
+ 3
+ 1
+
+
+ PR4
+ Pending bit 4
+ 4
+ 1
+
+
+ PR5
+ Pending bit 5
+ 5
+ 1
+
+
+ PR6
+ Pending bit 6
+ 6
+ 1
+
+
+ PR7
+ Pending bit 7
+ 7
+ 1
+
+
+ PR8
+ Pending bit 8
+ 8
+ 1
+
+
+ PR9
+ Pending bit 9
+ 9
+ 1
+
+
+ PR10
+ Pending bit 10
+ 10
+ 1
+
+
+ PR11
+ Pending bit 11
+ 11
+ 1
+
+
+ PR12
+ Pending bit 12
+ 12
+ 1
+
+
+ PR13
+ Pending bit 13
+ 13
+ 1
+
+
+ PR14
+ Pending bit 14
+ 14
+ 1
+
+
+ PR15
+ Pending bit 15
+ 15
+ 1
+
+
+ PR16
+ Pending bit 16
+ 16
+ 1
+
+
+ PR17
+ Pending bit 17
+ 17
+ 1
+
+
+ PR18
+ Pending bit 18
+ 18
+ 1
+
+
+
+
+
+
+ DMA1
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA1 Channel1 global interrupt
+ 11
+
+
+ DMA1_Channel2
+ DMA1 Channel2 global interrupt
+ 12
+
+
+ DMA1_Channel3
+ DMA1 Channel3 global interrupt
+ 13
+
+
+ DMA1_Channel4
+ DMA1 Channel4 global interrupt
+ 14
+
+
+ DMA1_Channel5
+ DMA1 Channel5 global interrupt
+ 15
+
+
+ DMA1_Channel6
+ DMA1 Channel6 global interrupt
+ 16
+
+
+ DMA1_Channel7
+ DMA1 Channel7 global interrupt
+ 17
+
+
+
+ ISR
+ ISR
+ DMA interrupt status register
+ (DMA_ISR)
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF1
+ Channel 1 Global interrupt
+ flag
+ 0
+ 1
+
+
+ TCIF1
+ Channel 1 Transfer Complete
+ flag
+ 1
+ 1
+
+
+ HTIF1
+ Channel 1 Half Transfer Complete
+ flag
+ 2
+ 1
+
+
+ TEIF1
+ Channel 1 Transfer Error
+ flag
+ 3
+ 1
+
+
+ GIF2
+ Channel 2 Global interrupt
+ flag
+ 4
+ 1
+
+
+ TCIF2
+ Channel 2 Transfer Complete
+ flag
+ 5
+ 1
+
+
+ HTIF2
+ Channel 2 Half Transfer Complete
+ flag
+ 6
+ 1
+
+
+ TEIF2
+ Channel 2 Transfer Error
+ flag
+ 7
+ 1
+
+
+ GIF3
+ Channel 3 Global interrupt
+ flag
+ 8
+ 1
+
+
+ TCIF3
+ Channel 3 Transfer Complete
+ flag
+ 9
+ 1
+
+
+ HTIF3
+ Channel 3 Half Transfer Complete
+ flag
+ 10
+ 1
+
+
+ TEIF3
+ Channel 3 Transfer Error
+ flag
+ 11
+ 1
+
+
+ GIF4
+ Channel 4 Global interrupt
+ flag
+ 12
+ 1
+
+
+ TCIF4
+ Channel 4 Transfer Complete
+ flag
+ 13
+ 1
+
+
+ HTIF4
+ Channel 4 Half Transfer Complete
+ flag
+ 14
+ 1
+
+
+ TEIF4
+ Channel 4 Transfer Error
+ flag
+ 15
+ 1
+
+
+ GIF5
+ Channel 5 Global interrupt
+ flag
+ 16
+ 1
+
+
+ TCIF5
+ Channel 5 Transfer Complete
+ flag
+ 17
+ 1
+
+
+ HTIF5
+ Channel 5 Half Transfer Complete
+ flag
+ 18
+ 1
+
+
+ TEIF5
+ Channel 5 Transfer Error
+ flag
+ 19
+ 1
+
+
+ GIF6
+ Channel 6 Global interrupt
+ flag
+ 20
+ 1
+
+
+ TCIF6
+ Channel 6 Transfer Complete
+ flag
+ 21
+ 1
+
+
+ HTIF6
+ Channel 6 Half Transfer Complete
+ flag
+ 22
+ 1
+
+
+ TEIF6
+ Channel 6 Transfer Error
+ flag
+ 23
+ 1
+
+
+ GIF7
+ Channel 7 Global interrupt
+ flag
+ 24
+ 1
+
+
+ TCIF7
+ Channel 7 Transfer Complete
+ flag
+ 25
+ 1
+
+
+ HTIF7
+ Channel 7 Half Transfer Complete
+ flag
+ 26
+ 1
+
+
+ TEIF7
+ Channel 7 Transfer Error
+ flag
+ 27
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ DMA interrupt flag clear register
+ (DMA_IFCR)
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Channel 1 Global interrupt
+ clear
+ 0
+ 1
+
+
+ CGIF2
+ Channel 2 Global interrupt
+ clear
+ 4
+ 1
+
+
+ CGIF3
+ Channel 3 Global interrupt
+ clear
+ 8
+ 1
+
+
+ CGIF4
+ Channel 4 Global interrupt
+ clear
+ 12
+ 1
+
+
+ CGIF5
+ Channel 5 Global interrupt
+ clear
+ 16
+ 1
+
+
+ CGIF6
+ Channel 6 Global interrupt
+ clear
+ 20
+ 1
+
+
+ CGIF7
+ Channel 7 Global interrupt
+ clear
+ 24
+ 1
+
+
+ CTCIF1
+ Channel 1 Transfer Complete
+ clear
+ 1
+ 1
+
+
+ CTCIF2
+ Channel 2 Transfer Complete
+ clear
+ 5
+ 1
+
+
+ CTCIF3
+ Channel 3 Transfer Complete
+ clear
+ 9
+ 1
+
+
+ CTCIF4
+ Channel 4 Transfer Complete
+ clear
+ 13
+ 1
+
+
+ CTCIF5
+ Channel 5 Transfer Complete
+ clear
+ 17
+ 1
+
+
+ CTCIF6
+ Channel 6 Transfer Complete
+ clear
+ 21
+ 1
+
+
+ CTCIF7
+ Channel 7 Transfer Complete
+ clear
+ 25
+ 1
+
+
+ CHTIF1
+ Channel 1 Half Transfer
+ clear
+ 2
+ 1
+
+
+ CHTIF2
+ Channel 2 Half Transfer
+ clear
+ 6
+ 1
+
+
+ CHTIF3
+ Channel 3 Half Transfer
+ clear
+ 10
+ 1
+
+
+ CHTIF4
+ Channel 4 Half Transfer
+ clear
+ 14
+ 1
+
+
+ CHTIF5
+ Channel 5 Half Transfer
+ clear
+ 18
+ 1
+
+
+ CHTIF6
+ Channel 6 Half Transfer
+ clear
+ 22
+ 1
+
+
+ CHTIF7
+ Channel 7 Half Transfer
+ clear
+ 26
+ 1
+
+
+ CTEIF1
+ Channel 1 Transfer Error
+ clear
+ 3
+ 1
+
+
+ CTEIF2
+ Channel 2 Transfer Error
+ clear
+ 7
+ 1
+
+
+ CTEIF3
+ Channel 3 Transfer Error
+ clear
+ 11
+ 1
+
+
+ CTEIF4
+ Channel 4 Transfer Error
+ clear
+ 15
+ 1
+
+
+ CTEIF5
+ Channel 5 Transfer Error
+ clear
+ 19
+ 1
+
+
+ CTEIF6
+ Channel 6 Transfer Error
+ clear
+ 23
+ 1
+
+
+ CTEIF7
+ Channel 7 Transfer Error
+ clear
+ 27
+ 1
+
+
+
+
+ CCR1
+ CCR1
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR1
+ CNDTR1
+ DMA channel 1 number of data
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR1
+ CPAR1
+ DMA channel 1 peripheral address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR1
+ CMAR1
+ DMA channel 1 memory address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR2
+ CCR2
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR2
+ CNDTR2
+ DMA channel 2 number of data
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR2
+ CPAR2
+ DMA channel 2 peripheral address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR2
+ CMAR2
+ DMA channel 2 memory address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR3
+ CCR3
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR3
+ CNDTR3
+ DMA channel 3 number of data
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR3
+ CPAR3
+ DMA channel 3 peripheral address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR3
+ CMAR3
+ DMA channel 3 memory address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR4
+ CCR4
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR4
+ CNDTR4
+ DMA channel 4 number of data
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR4
+ CPAR4
+ DMA channel 4 peripheral address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR4
+ CMAR4
+ DMA channel 4 memory address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR5
+ CCR5
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR5
+ CNDTR5
+ DMA channel 5 number of data
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR5
+ CPAR5
+ DMA channel 5 peripheral address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR5
+ CMAR5
+ DMA channel 5 memory address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR6
+ CCR6
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR6
+ CNDTR6
+ DMA channel 6 number of data
+ register
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR6
+ CPAR6
+ DMA channel 6 peripheral address
+ register
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR6
+ CMAR6
+ DMA channel 6 memory address
+ register
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ CCR7
+ CCR7
+ DMA channel configuration register
+ (DMA_CCR)
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half Transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel Priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CNDTR7
+ CNDTR7
+ DMA channel 7 number of data
+ register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ CPAR7
+ CPAR7
+ DMA channel 7 peripheral address
+ register
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CMAR7
+ CMAR7
+ DMA channel 7 memory address
+ register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ DMA2
+ 0x40020400
+
+ DMA2_Channel1
+ DMA2 Channel1 global interrupt
+ 56
+
+
+ DMA2_Channel2
+ DMA2 Channel2 global interrupt
+ 57
+
+
+ DMA2_Channel3
+ DMA2 Channel3 global interrupt
+ 58
+
+
+ DMA2_Channel4_5
+ DMA2 Channel4 and DMA2 Channel5 global
+ interrupt
+ 59
+
+
+
+ SDIO
+ Secure digital input/output
+ interface
+ SDIO
+ 0x40018000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SDIO
+ SDIO global interrupt
+ 49
+
+
+
+ POWER
+ POWER
+ Bits 1:0 = PWRCTRL: Power supply control
+ bits
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PWRCTRL
+ PWRCTRL
+ 0
+ 2
+
+
+
+
+ CLKCR
+ CLKCR
+ SDI clock control register
+ (SDIO_CLKCR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLKDIV
+ Clock divide factor
+ 0
+ 8
+
+
+ CLKEN
+ Clock enable bit
+ 8
+ 1
+
+
+ PWRSAV
+ Power saving configuration
+ bit
+ 9
+ 1
+
+
+ BYPASS
+ Clock divider bypass enable
+ bit
+ 10
+ 1
+
+
+ WIDBUS
+ Wide bus mode enable bit
+ 11
+ 2
+
+
+ NEGEDGE
+ SDIO_CK dephasing selection
+ bit
+ 13
+ 1
+
+
+ HWFC_EN
+ HW Flow Control enable
+ 14
+ 1
+
+
+
+
+ ARG
+ ARG
+ Bits 31:0 = : Command argument
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CMDARG
+ Command argument
+ 0
+ 32
+
+
+
+
+ CMD
+ CMD
+ SDIO command register
+ (SDIO_CMD)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CMDINDEX
+ CMDINDEX
+ 0
+ 6
+
+
+ WAITRESP
+ WAITRESP
+ 6
+ 2
+
+
+ WAITINT
+ WAITINT
+ 8
+ 1
+
+
+ WAITPEND
+ WAITPEND
+ 9
+ 1
+
+
+ CPSMEN
+ CPSMEN
+ 10
+ 1
+
+
+ SDIOSuspend
+ SDIOSuspend
+ 11
+ 1
+
+
+ ENCMDcompl
+ ENCMDcompl
+ 12
+ 1
+
+
+ nIEN
+ nIEN
+ 13
+ 1
+
+
+ CE_ATACMD
+ CE_ATACMD
+ 14
+ 1
+
+
+
+
+ RESPCMD
+ RESPCMD
+ SDIO command register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RESPCMD
+ RESPCMD
+ 0
+ 6
+
+
+
+
+ RESPI1
+ RESPI1
+ Bits 31:0 = CARDSTATUS1
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CARDSTATUS1
+ CARDSTATUS1
+ 0
+ 32
+
+
+
+
+ RESP2
+ RESP2
+ Bits 31:0 = CARDSTATUS2
+ 0x18
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CARDSTATUS2
+ CARDSTATUS2
+ 0
+ 32
+
+
+
+
+ RESP3
+ RESP3
+ Bits 31:0 = CARDSTATUS3
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CARDSTATUS3
+ CARDSTATUS3
+ 0
+ 32
+
+
+
+
+ RESP4
+ RESP4
+ Bits 31:0 = CARDSTATUS4
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CARDSTATUS4
+ CARDSTATUS4
+ 0
+ 32
+
+
+
+
+ DTIMER
+ DTIMER
+ Bits 31:0 = DATATIME: Data timeout
+ period
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATATIME
+ Data timeout period
+ 0
+ 32
+
+
+
+
+ DLEN
+ DLEN
+ Bits 24:0 = DATALENGTH: Data length
+ value
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATALENGTH
+ Data length value
+ 0
+ 25
+
+
+
+
+ DCTRL
+ DCTRL
+ SDIO data control register
+ (SDIO_DCTRL)
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DTEN
+ DTEN
+ 0
+ 1
+
+
+ DTDIR
+ DTDIR
+ 1
+ 1
+
+
+ DTMODE
+ DTMODE
+ 2
+ 1
+
+
+ DMAEN
+ DMAEN
+ 3
+ 1
+
+
+ DBLOCKSIZE
+ DBLOCKSIZE
+ 4
+ 4
+
+
+ PWSTART
+ PWSTART
+ 8
+ 1
+
+
+ PWSTOP
+ PWSTOP
+ 9
+ 1
+
+
+ RWMOD
+ RWMOD
+ 10
+ 1
+
+
+ SDIOEN
+ SDIOEN
+ 11
+ 1
+
+
+
+
+ DCOUNT
+ DCOUNT
+ Bits 24:0 = DATACOUNT: Data count
+ value
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATACOUNT
+ Data count value
+ 0
+ 25
+
+
+
+
+ STA
+ STA
+ SDIO status register
+ (SDIO_STA)
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ CCRCFAIL
+ CCRCFAIL
+ 0
+ 1
+
+
+ DCRCFAIL
+ DCRCFAIL
+ 1
+ 1
+
+
+ CTIMEOUT
+ CTIMEOUT
+ 2
+ 1
+
+
+ DTIMEOUT
+ DTIMEOUT
+ 3
+ 1
+
+
+ TXUNDERR
+ TXUNDERR
+ 4
+ 1
+
+
+ RXOVERR
+ RXOVERR
+ 5
+ 1
+
+
+ CMDREND
+ CMDREND
+ 6
+ 1
+
+
+ CMDSENT
+ CMDSENT
+ 7
+ 1
+
+
+ DATAEND
+ DATAEND
+ 8
+ 1
+
+
+ STBITERR
+ STBITERR
+ 9
+ 1
+
+
+ DBCKEND
+ DBCKEND
+ 10
+ 1
+
+
+ CMDACT
+ CMDACT
+ 11
+ 1
+
+
+ TXACT
+ TXACT
+ 12
+ 1
+
+
+ RXACT
+ RXACT
+ 13
+ 1
+
+
+ TXFIFOHE
+ TXFIFOHE
+ 14
+ 1
+
+
+ RXFIFOHF
+ RXFIFOHF
+ 15
+ 1
+
+
+ TXFIFOF
+ TXFIFOF
+ 16
+ 1
+
+
+ RXFIFOF
+ RXFIFOF
+ 17
+ 1
+
+
+ TXFIFOE
+ TXFIFOE
+ 18
+ 1
+
+
+ RXFIFOE
+ RXFIFOE
+ 19
+ 1
+
+
+ TXDAVL
+ TXDAVL
+ 20
+ 1
+
+
+ RXDAVL
+ RXDAVL
+ 21
+ 1
+
+
+ SDIOIT
+ SDIOIT
+ 22
+ 1
+
+
+ CEATAEND
+ CEATAEND
+ 23
+ 1
+
+
+
+
+ ICR
+ ICR
+ SDIO interrupt clear register
+ (SDIO_ICR)
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCRCFAILC
+ CCRCFAILC
+ 0
+ 1
+
+
+ DCRCFAILC
+ DCRCFAILC
+ 1
+ 1
+
+
+ CTIMEOUTC
+ CTIMEOUTC
+ 2
+ 1
+
+
+ DTIMEOUTC
+ DTIMEOUTC
+ 3
+ 1
+
+
+ TXUNDERRC
+ TXUNDERRC
+ 4
+ 1
+
+
+ RXOVERRC
+ RXOVERRC
+ 5
+ 1
+
+
+ CMDRENDC
+ CMDRENDC
+ 6
+ 1
+
+
+ CMDSENTC
+ CMDSENTC
+ 7
+ 1
+
+
+ DATAENDC
+ DATAENDC
+ 8
+ 1
+
+
+ STBITERRC
+ STBITERRC
+ 9
+ 1
+
+
+ DBCKENDC
+ DBCKENDC
+ 10
+ 1
+
+
+ SDIOITC
+ SDIOITC
+ 22
+ 1
+
+
+ CEATAENDC
+ CEATAENDC
+ 23
+ 1
+
+
+
+
+ MASK
+ MASK
+ SDIO mask register (SDIO_MASK)
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCRCFAILIE
+ CCRCFAILIE
+ 0
+ 1
+
+
+ DCRCFAILIE
+ DCRCFAILIE
+ 1
+ 1
+
+
+ CTIMEOUTIE
+ CTIMEOUTIE
+ 2
+ 1
+
+
+ DTIMEOUTIE
+ DTIMEOUTIE
+ 3
+ 1
+
+
+ TXUNDERRIE
+ TXUNDERRIE
+ 4
+ 1
+
+
+ RXOVERRIE
+ RXOVERRIE
+ 5
+ 1
+
+
+ CMDRENDIE
+ CMDRENDIE
+ 6
+ 1
+
+
+ CMDSENTIE
+ CMDSENTIE
+ 7
+ 1
+
+
+ DATAENDIE
+ DATAENDIE
+ 8
+ 1
+
+
+ STBITERRIE
+ STBITERRIE
+ 9
+ 1
+
+
+ DBACKENDIE
+ DBACKENDIE
+ 10
+ 1
+
+
+ CMDACTIE
+ CMDACTIE
+ 11
+ 1
+
+
+ TXACTIE
+ TXACTIE
+ 12
+ 1
+
+
+ RXACTIE
+ RXACTIE
+ 13
+ 1
+
+
+ TXFIFOHEIE
+ TXFIFOHEIE
+ 14
+ 1
+
+
+ RXFIFOHFIE
+ RXFIFOHFIE
+ 15
+ 1
+
+
+ TXFIFOFIE
+ TXFIFOFIE
+ 16
+ 1
+
+
+ RXFIFOFIE
+ RXFIFOFIE
+ 17
+ 1
+
+
+ TXFIFOEIE
+ TXFIFOEIE
+ 18
+ 1
+
+
+ RXFIFOEIE
+ RXFIFOEIE
+ 19
+ 1
+
+
+ TXDAVLIE
+ TXDAVLIE
+ 20
+ 1
+
+
+ RXDAVLIE
+ RXDAVLIE
+ 21
+ 1
+
+
+ SDIOITIE
+ SDIOITIE
+ 22
+ 1
+
+
+ CEATENDIE
+ CEATENDIE
+ 23
+ 1
+
+
+
+
+ FIFOCNT
+ FIFOCNT
+ Bits 23:0 = FIFOCOUNT: Remaining number of
+ words to be written to or read from the
+ FIFO
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ FIF0COUNT
+ FIF0COUNT
+ 0
+ 24
+
+
+
+
+ FIFO
+ FIFO
+ bits 31:0 = FIFOData: Receive and transmit
+ FIFO data
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FIFOData
+ FIFOData
+ 0
+ 32
+
+
+
+
+
+
+ RTC
+ Real time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 3
+
+
+ RTCAlarm
+ RTC Alarms through EXTI line
+ interrupt
+ 41
+
+
+
+ CRH
+ CRH
+ RTC Control Register High
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SECIE
+ Second interrupt Enable
+ 0
+ 1
+
+
+ ALRIE
+ Alarm interrupt Enable
+ 1
+ 1
+
+
+ OWIE
+ Overflow interrupt Enable
+ 2
+ 1
+
+
+
+
+ CRL
+ CRL
+ RTC Control Register Low
+ 0x4
+ 0x20
+ 0x00000020
+
+
+ SECF
+ Second Flag
+ 0
+ 1
+ read-write
+
+
+ ALRF
+ Alarm Flag
+ 1
+ 1
+ read-write
+
+
+ OWF
+ Overflow Flag
+ 2
+ 1
+ read-write
+
+
+ RSF
+ Registers Synchronized
+ Flag
+ 3
+ 1
+ read-write
+
+
+ CNF
+ Configuration Flag
+ 4
+ 1
+ read-write
+
+
+ RTOFF
+ RTC operation OFF
+ 5
+ 1
+ read-only
+
+
+
+
+ PRLH
+ PRLH
+ RTC Prescaler Load Register
+ High
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ PRLH
+ RTC Prescaler Load Register
+ High
+ 0
+ 4
+
+
+
+
+ PRLL
+ PRLL
+ RTC Prescaler Load Register
+ Low
+ 0xC
+ 0x20
+ write-only
+ 0x8000
+
+
+ PRLL
+ RTC Prescaler Divider Register
+ Low
+ 0
+ 16
+
+
+
+
+ DIVH
+ DIVH
+ RTC Prescaler Divider Register
+ High
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DIVH
+ RTC prescaler divider register
+ high
+ 0
+ 4
+
+
+
+
+ DIVL
+ DIVL
+ RTC Prescaler Divider Register
+ Low
+ 0x14
+ 0x20
+ read-only
+ 0x8000
+
+
+ DIVL
+ RTC prescaler divider register
+ Low
+ 0
+ 16
+
+
+
+
+ CNTH
+ CNTH
+ RTC Counter Register High
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTH
+ RTC counter register high
+ 0
+ 16
+
+
+
+
+ CNTL
+ CNTL
+ RTC Counter Register Low
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNTL
+ RTC counter register Low
+ 0
+ 16
+
+
+
+
+ ALRH
+ ALRH
+ RTC Alarm Register High
+ 0x20
+ 0x20
+ write-only
+ 0xFFFF
+
+
+ ALRH
+ RTC alarm register high
+ 0
+ 16
+
+
+
+
+ ALRL
+ ALRL
+ RTC Alarm Register Low
+ 0x24
+ 0x20
+ write-only
+ 0xFFFF
+
+
+ ALRL
+ RTC alarm register low
+ 0
+ 16
+
+
+
+
+
+
+ BKP
+ Backup registers
+ BKP
+ 0x40006C04
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR1
+ DR1
+ Backup data register (BKP_DR)
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D1
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR2
+ DR2
+ Backup data register (BKP_DR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D2
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR3
+ DR3
+ Backup data register (BKP_DR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D3
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR4
+ DR4
+ Backup data register (BKP_DR)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D4
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR5
+ DR5
+ Backup data register (BKP_DR)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D5
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR6
+ DR6
+ Backup data register (BKP_DR)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D6
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR7
+ DR7
+ Backup data register (BKP_DR)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D7
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR8
+ DR8
+ Backup data register (BKP_DR)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D8
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR9
+ DR9
+ Backup data register (BKP_DR)
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D9
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR10
+ DR10
+ Backup data register (BKP_DR)
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D10
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR11
+ DR11
+ Backup data register (BKP_DR)
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR11
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR12
+ DR12
+ Backup data register (BKP_DR)
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR12
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR13
+ DR13
+ Backup data register (BKP_DR)
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR13
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR14
+ DR14
+ Backup data register (BKP_DR)
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D14
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR15
+ DR15
+ Backup data register (BKP_DR)
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D15
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR16
+ DR16
+ Backup data register (BKP_DR)
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D16
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR17
+ DR17
+ Backup data register (BKP_DR)
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D17
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR18
+ DR18
+ Backup data register (BKP_DR)
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D18
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR19
+ DR19
+ Backup data register (BKP_DR)
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D19
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR20
+ DR20
+ Backup data register (BKP_DR)
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D20
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR21
+ DR21
+ Backup data register (BKP_DR)
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D21
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR22
+ DR22
+ Backup data register (BKP_DR)
+ 0x68
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D22
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR23
+ DR23
+ Backup data register (BKP_DR)
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D23
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR24
+ DR24
+ Backup data register (BKP_DR)
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D24
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR25
+ DR25
+ Backup data register (BKP_DR)
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D25
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR26
+ DR26
+ Backup data register (BKP_DR)
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D26
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR27
+ DR27
+ Backup data register (BKP_DR)
+ 0x7C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D27
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR28
+ DR28
+ Backup data register (BKP_DR)
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D28
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR29
+ DR29
+ Backup data register (BKP_DR)
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D29
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR30
+ DR30
+ Backup data register (BKP_DR)
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D30
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR31
+ DR31
+ Backup data register (BKP_DR)
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D31
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR32
+ DR32
+ Backup data register (BKP_DR)
+ 0x90
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D32
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR33
+ DR33
+ Backup data register (BKP_DR)
+ 0x94
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D33
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR34
+ DR34
+ Backup data register (BKP_DR)
+ 0x98
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D34
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR35
+ DR35
+ Backup data register (BKP_DR)
+ 0x9C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D35
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR36
+ DR36
+ Backup data register (BKP_DR)
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D36
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR37
+ DR37
+ Backup data register (BKP_DR)
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D37
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR38
+ DR38
+ Backup data register (BKP_DR)
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D38
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR39
+ DR39
+ Backup data register (BKP_DR)
+ 0xAC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D39
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR40
+ DR40
+ Backup data register (BKP_DR)
+ 0xB0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D40
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR41
+ DR41
+ Backup data register (BKP_DR)
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D41
+ Backup data
+ 0
+ 16
+
+
+
+
+ DR42
+ DR42
+ Backup data register (BKP_DR)
+ 0xB8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ D42
+ Backup data
+ 0
+ 16
+
+
+
+
+ RTCCR
+ RTCCR
+ RTC clock calibration register
+ (BKP_RTCCR)
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CAL
+ Calibration value
+ 0
+ 7
+
+
+ CCO
+ Calibration Clock Output
+ 7
+ 1
+
+
+ ASOE
+ Alarm or second output
+ enable
+ 8
+ 1
+
+
+ ASOS
+ Alarm or second output
+ selection
+ 9
+ 1
+
+
+
+
+ CR
+ CR
+ Backup control register
+ (BKP_CR)
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TPE
+ Tamper pin enable
+ 0
+ 1
+
+
+ TPAL
+ Tamper pin active level
+ 1
+ 1
+
+
+
+
+ CSR
+ CSR
+ BKP_CSR control/status register
+ (BKP_CSR)
+ 0x30
+ 0x20
+ 0x00000000
+
+
+ CTE
+ Clear Tamper event
+ 0
+ 1
+ write-only
+
+
+ CTI
+ Clear Tamper Interrupt
+ 1
+ 1
+ write-only
+
+
+ TPIE
+ Tamper Pin interrupt
+ enable
+ 2
+ 1
+ read-write
+
+
+ TEF
+ Tamper Event Flag
+ 8
+ 1
+ read-only
+
+
+ TIF
+ Tamper Interrupt Flag
+ 9
+ 1
+ read-only
+
+
+
+
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register (IWDG_KR)
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register (IWDG_PR)
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register (IWDG_RLR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register (IWDG_SR)
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+
+
+
+
+ WWDG
+ Window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window Watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register (WWDG_CR)
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ T
+ 7-bit counter (MSB to LSB)
+ 0
+ 7
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ (WWDG_CFR)
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+ WDGTB
+ Timer Base
+ 7
+ 2
+
+
+ EWI
+ Early Wakeup Interrupt
+ 9
+ 1
+
+
+
+
+ SR
+ SR
+ Status register (WWDG_SR)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWI
+ Early Wakeup Interrupt
+ 0
+ 1
+
+
+
+
+
+
+ TIM1
+ Advanced timer
+ TIM
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_TIM9
+ TIM1 Break interrupt and TIM9 global
+ interrupt
+ 24
+
+
+ TIM1_UP_TIM10
+ TIM1 Update interrupt and TIM10 global
+ interrupt
+ 25
+
+
+ TIM1_TRG_COM_TIM11
+ TIM1 Trigger and Commutation interrupts and
+ TIM11 global interrupt
+ 26
+
+
+ TIM1_CC
+ TIM1 Capture Compare interrupt
+ 27
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ OIS4
+ Output Idle state 4
+ 14
+ 1
+
+
+ OIS3N
+ Output Idle state 3
+ 13
+ 1
+
+
+ OIS3
+ Output Idle state 3
+ 12
+ 1
+
+
+ OIS2N
+ Output Idle state 2
+ 11
+ 1
+
+
+ OIS2
+ Output Idle state 2
+ 10
+ 1
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output Compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output Compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PCS
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ ICPCS
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC3NE
+ Capture/Compare 3 complementary output
+ enable
+ 10
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2NE
+ Capture/Compare 2 complementary output
+ enable
+ 6
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+
+
+
+
+ TIM8
+ 0x40013400
+
+ TIM8_BRK_TIM12
+ TIM8 Break interrupt and TIM12 global
+ interrupt
+ 43
+
+
+ TIM8_UP_TIM13
+ TIM8 Update interrupt and TIM13 global
+ interrupt
+ 44
+
+
+ TIM8_TRG_COM_TIM14
+ TIM8 Trigger and Commutation interrupts and
+ TIM14 global interrupt
+ 45
+
+
+ TIM8_CC
+ TIM8 Capture Compare interrupt
+ 46
+
+
+
+ TIM2
+ General purpose timer
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM2
+ TIM2 global interrupt
+ 28
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ O24CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM3
+ TIM3 global interrupt
+ 29
+
+
+
+ TIM4
+ 0x40000800
+
+ TIM4
+ TIM4 global interrupt
+ 30
+
+
+
+ TIM5
+ 0x40000C00
+
+ TIM5
+ TIM5 global interrupt
+ 50
+
+
+
+ TIM9
+ General purpose timer
+ TIM
+ 0x40014C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_TIM9
+ TIM1 Break interrupt and TIM9 global
+ interrupt
+ 24
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+
+
+ TIM12
+ 0x40001800
+
+ TIM8_BRK_TIM12
+ TIM8 Break interrupt and TIM12 global
+ interrupt
+ 43
+
+
+
+ TIM10
+ General purpose timer
+ TIM
+ 0x40015000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_UP_TIM10
+ TIM1 Update interrupt and TIM10 global
+ interrupt
+ 25
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+
+
+ TIM11
+ 0x40015400
+
+ TIM1_TRG_COM_TIM11
+ TIM1 Trigger and Commutation interrupts and
+ TIM11 global interrupt
+ 26
+
+
+
+ TIM13
+ 0x40001C00
+
+ TIM8_UP_TIM13
+ TIM8 Update interrupt and TIM13 global
+ interrupt
+ 44
+
+
+
+ TIM14
+ 0x40002000
+
+ TIM8_TRG_COM_TIM14
+ TIM8 Trigger and Commutation interrupts and
+ TIM14 global interrupt
+ 45
+
+
+
+ TIM6
+ Basic timer
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt
+ 54
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM7
+ 0x40001400
+
+ TIM7
+ TIM7 global interrupt
+ 55
+
+
+
+ I2C1
+ Inter integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1_EV
+ I2C1 event interrupt
+ 31
+
+
+ I2C1_ER
+ I2C1 error interrupt
+ 32
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SWRST
+ Software reset
+ 15
+ 1
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+
+
+ PEC
+ Packet error checking
+ 12
+ 1
+
+
+ POS
+ Acknowledge/PEC Position (for data
+ reception)
+ 11
+ 1
+
+
+ ACK
+ Acknowledge enable
+ 10
+ 1
+
+
+ STOP
+ Stop generation
+ 9
+ 1
+
+
+ START
+ Start generation
+ 8
+ 1
+
+
+ NOSTRETCH
+ Clock stretching disable (Slave
+ mode)
+ 7
+ 1
+
+
+ ENGC
+ General call enable
+ 6
+ 1
+
+
+ ENPEC
+ PEC enable
+ 5
+ 1
+
+
+ ENARP
+ ARP enable
+ 4
+ 1
+
+
+ SMBTYPE
+ SMBus type
+ 3
+ 1
+
+
+ SMBUS
+ SMBus mode
+ 1
+ 1
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ LAST
+ DMA last transfer
+ 12
+ 1
+
+
+ DMAEN
+ DMA requests enable
+ 11
+ 1
+
+
+ ITBUFEN
+ Buffer interrupt enable
+ 10
+ 1
+
+
+ ITEVTEN
+ Event interrupt enable
+ 9
+ 1
+
+
+ ITERREN
+ Error interrupt enable
+ 8
+ 1
+
+
+ FREQ
+ Peripheral clock frequency
+ 0
+ 6
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADDMODE
+ Addressing mode (slave
+ mode)
+ 15
+ 1
+
+
+ ADD10
+ Interface address
+ 8
+ 2
+
+
+ ADD7
+ Interface address
+ 1
+ 7
+
+
+ ADD0
+ Interface address
+ 0
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD2
+ Interface address
+ 1
+ 7
+
+
+ ENDUAL
+ Dual addressing mode
+ enable
+ 0
+ 1
+
+
+
+
+ DR
+ DR
+ Data register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ 8-bit data register
+ 0
+ 8
+
+
+
+
+ SR1
+ SR1
+ Status register 1
+ 0x14
+ 0x20
+ 0x0000
+
+
+ SMBALERT
+ SMBus alert
+ 15
+ 1
+ read-write
+
+
+ TIMEOUT
+ Timeout or Tlow error
+ 14
+ 1
+ read-write
+
+
+ PECERR
+ PEC Error in reception
+ 12
+ 1
+ read-write
+
+
+ OVR
+ Overrun/Underrun
+ 11
+ 1
+ read-write
+
+
+ AF
+ Acknowledge failure
+ 10
+ 1
+ read-write
+
+
+ ARLO
+ Arbitration lost (master
+ mode)
+ 9
+ 1
+ read-write
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-write
+
+
+ TxE
+ Data register empty
+ (transmitters)
+ 7
+ 1
+ read-only
+
+
+ RxNE
+ Data register not empty
+ (receivers)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection (slave
+ mode)
+ 4
+ 1
+ read-only
+
+
+ ADD10
+ 10-bit header sent (Master
+ mode)
+ 3
+ 1
+ read-only
+
+
+ BTF
+ Byte transfer finished
+ 2
+ 1
+ read-only
+
+
+ ADDR
+ Address sent (master mode)/matched
+ (slave mode)
+ 1
+ 1
+ read-only
+
+
+ SB
+ Start bit (Master mode)
+ 0
+ 1
+ read-only
+
+
+
+
+ SR2
+ SR2
+ Status register 2
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ PEC
+ acket error checking
+ register
+ 8
+ 8
+
+
+ DUALF
+ Dual flag (Slave mode)
+ 7
+ 1
+
+
+ SMBHOST
+ SMBus host header (Slave
+ mode)
+ 6
+ 1
+
+
+ SMBDEFAULT
+ SMBus device default address (Slave
+ mode)
+ 5
+ 1
+
+
+ GENCALL
+ General call address (Slave
+ mode)
+ 4
+ 1
+
+
+ TRA
+ Transmitter/receiver
+ 2
+ 1
+
+
+ BUSY
+ Bus busy
+ 1
+ 1
+
+
+ MSL
+ Master/slave
+ 0
+ 1
+
+
+
+
+ CCR
+ CCR
+ Clock control register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ F_S
+ I2C master mode selection
+ 15
+ 1
+
+
+ DUTY
+ Fast mode duty cycle
+ 14
+ 1
+
+
+ CCR
+ Clock control register in Fast/Standard
+ mode (Master mode)
+ 0
+ 12
+
+
+
+
+ TRISE
+ TRISE
+ TRISE register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ TRISE
+ Maximum rise time in Fast/Standard mode
+ (Master mode)
+ 0
+ 6
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2_EV
+ I2C2 event interrupt
+ 33
+
+
+ I2C2_ER
+ I2C2 error interrupt
+ 34
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1 global interrupt
+ 35
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ DFF
+ Data frame format
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x0002
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SE
+ I2S Enable
+ 10
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPOL
+ Steady state clock
+ polarity
+ 3
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 00000010
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ I2SDIV
+ I2S Linear prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 36
+
+
+
+ SPI3
+ 0x40003C00
+
+ SPI3
+ SPI3 global interrupt
+ 51
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 37
+
+
+
+ SR
+ SR
+ Status register
+ 0x0
+ 0x20
+ 0x00C0
+
+
+ CTS
+ CTS flag
+ 9
+ 1
+ read-write
+
+
+ LBD
+ LIN break detection flag
+ 8
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register
+ empty
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transmission complete
+ 6
+ 1
+ read-write
+
+
+ RXNE
+ Read data register not
+ empty
+ 5
+ 1
+ read-write
+
+
+ IDLE
+ IDLE line detected
+ 4
+ 1
+ read-only
+
+
+ ORE
+ Overrun error
+ 3
+ 1
+ read-only
+
+
+ NE
+ Noise error flag
+ 2
+ 1
+ read-only
+
+
+ FE
+ Framing error
+ 1
+ 1
+ read-only
+
+
+ PE
+ Parity error
+ 0
+ 1
+ read-only
+
+
+
+
+ DR
+ DR
+ Data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DR
+ Data value
+ 0
+ 9
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ DIV_Mantissa
+ mantissa of USARTDIV
+ 4
+ 12
+
+
+ DIV_Fraction
+ fraction of USARTDIV
+ 0
+ 4
+
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UE
+ USART enable
+ 13
+ 1
+
+
+ M
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ TXE interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ RWU
+ Receiver wakeup
+ 1
+ 1
+
+
+ SBK
+ Send break
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ lin break detection length
+ 5
+ 1
+
+
+ ADD
+ Address of the USART node
+ 0
+ 4
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2
+ USART2 global interrupt
+ 38
+
+
+
+ USART3
+ 0x40004800
+
+ USART3
+ USART3 global interrupt
+ 39
+
+
+
+ ADC1
+ Analog to digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC
+ ADC1 global interrupt
+ 18
+
+
+
+ SR
+ SR
+ status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STRT
+ Regular channel start flag
+ 4
+ 1
+
+
+ JSTRT
+ Injected channel start
+ flag
+ 3
+ 1
+
+
+ JEOC
+ Injected channel end of
+ conversion
+ 2
+ 1
+
+
+ EOC
+ Regular channel end of
+ conversion
+ 1
+ 1
+
+
+ AWD
+ Analog watchdog flag
+ 0
+ 1
+
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDEN
+ Analog watchdog enable on regular
+ channels
+ 23
+ 1
+
+
+ JAWDEN
+ Analog watchdog enable on injected
+ channels
+ 22
+ 1
+
+
+ DUALMOD
+ Dual mode selection
+ 16
+ 4
+
+
+ DISCNUM
+ Discontinuous mode channel
+ count
+ 13
+ 3
+
+
+ JDISCEN
+ Discontinuous mode on injected
+ channels
+ 12
+ 1
+
+
+ DISCEN
+ Discontinuous mode on regular
+ channels
+ 11
+ 1
+
+
+ JAUTO
+ Automatic injected group
+ conversion
+ 10
+ 1
+
+
+ AWDSGL
+ Enable the watchdog on a single channel
+ in scan mode
+ 9
+ 1
+
+
+ SCAN
+ Scan mode
+ 8
+ 1
+
+
+ JEOCIE
+ Interrupt enable for injected
+ channels
+ 7
+ 1
+
+
+ AWDIE
+ Analog watchdog interrupt
+ enable
+ 6
+ 1
+
+
+ EOCIE
+ Interrupt enable for EOC
+ 5
+ 1
+
+
+ AWDCH
+ Analog watchdog channel select
+ bits
+ 0
+ 5
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TSVREFE
+ Temperature sensor and VREFINT
+ enable
+ 23
+ 1
+
+
+ SWSTART
+ Start conversion of regular
+ channels
+ 22
+ 1
+
+
+ JSWSTART
+ Start conversion of injected
+ channels
+ 21
+ 1
+
+
+ EXTTRIG
+ External trigger conversion mode for
+ regular channels
+ 20
+ 1
+
+
+ EXTSEL
+ External event select for regular
+ group
+ 17
+ 3
+
+
+ JEXTTRIG
+ External trigger conversion mode for
+ injected channels
+ 15
+ 1
+
+
+ JEXTSEL
+ External event select for injected
+ group
+ 12
+ 3
+
+
+ ALIGN
+ Data alignment
+ 11
+ 1
+
+
+ DMA
+ Direct memory access mode
+ 8
+ 1
+
+
+ RSTCAL
+ Reset calibration
+ 3
+ 1
+
+
+ CAL
+ A/D calibration
+ 2
+ 1
+
+
+ CONT
+ Continuous conversion
+ 1
+ 1
+
+
+ ADON
+ A/D converter ON / OFF
+ 0
+ 1
+
+
+
+
+ SMPR1
+ SMPR1
+ sample time register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP10
+ Channel 10 sample time
+ selection
+ 0
+ 3
+
+
+ SMP11
+ Channel 11 sample time
+ selection
+ 3
+ 3
+
+
+ SMP12
+ Channel 12 sample time
+ selection
+ 6
+ 3
+
+
+ SMP13
+ Channel 13 sample time
+ selection
+ 9
+ 3
+
+
+ SMP14
+ Channel 14 sample time
+ selection
+ 12
+ 3
+
+
+ SMP15
+ Channel 15 sample time
+ selection
+ 15
+ 3
+
+
+ SMP16
+ Channel 16 sample time
+ selection
+ 18
+ 3
+
+
+ SMP17
+ Channel 17 sample time
+ selection
+ 21
+ 3
+
+
+
+
+ SMPR2
+ SMPR2
+ sample time register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP0
+ Channel 0 sample time
+ selection
+ 0
+ 3
+
+
+ SMP1
+ Channel 1 sample time
+ selection
+ 3
+ 3
+
+
+ SMP2
+ Channel 2 sample time
+ selection
+ 6
+ 3
+
+
+ SMP3
+ Channel 3 sample time
+ selection
+ 9
+ 3
+
+
+ SMP4
+ Channel 4 sample time
+ selection
+ 12
+ 3
+
+
+ SMP5
+ Channel 5 sample time
+ selection
+ 15
+ 3
+
+
+ SMP6
+ Channel 6 sample time
+ selection
+ 18
+ 3
+
+
+ SMP7
+ Channel 7 sample time
+ selection
+ 21
+ 3
+
+
+ SMP8
+ Channel 8 sample time
+ selection
+ 24
+ 3
+
+
+ SMP9
+ Channel 9 sample time
+ selection
+ 27
+ 3
+
+
+
+
+ JOFR1
+ JOFR1
+ injected channel data offset register
+ x
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET1
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR2
+ JOFR2
+ injected channel data offset register
+ x
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET2
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR3
+ JOFR3
+ injected channel data offset register
+ x
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET3
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR4
+ JOFR4
+ injected channel data offset register
+ x
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET4
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ HTR
+ HTR
+ watchdog higher threshold
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ HT
+ Analog watchdog higher
+ threshold
+ 0
+ 12
+
+
+
+
+ LTR
+ LTR
+ watchdog lower threshold
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ SQR1
+ SQR1
+ regular sequence register 1
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ L
+ Regular channel sequence
+ length
+ 20
+ 4
+
+
+ SQ16
+ 16th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ15
+ 15th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ14
+ 14th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ13
+ 13th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ SQR2
+ SQR2
+ regular sequence register 2
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ12
+ 12th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ SQ11
+ 11th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ SQ10
+ 10th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ9
+ 9th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ8
+ 8th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ7
+ 7th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ SQR3
+ SQR3
+ regular sequence register 3
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ6
+ 6th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ SQ5
+ 5th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ SQ4
+ 4th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ3
+ 3rd conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ2
+ 2nd conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ1
+ 1st conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ JSQR
+ JSQR
+ injected sequence register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JL
+ Injected sequence length
+ 20
+ 2
+
+
+ JSQ4
+ 4th conversion in injected
+ sequence
+ 15
+ 5
+
+
+ JSQ3
+ 3rd conversion in injected
+ sequence
+ 10
+ 5
+
+
+ JSQ2
+ 2nd conversion in injected
+ sequence
+ 5
+ 5
+
+
+ JSQ1
+ 1st conversion in injected
+ sequence
+ 0
+ 5
+
+
+
+
+ JDR1
+ JDR1
+ injected data register x
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR2
+ JDR2
+ injected data register x
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR3
+ JDR3
+ injected data register x
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR4
+ JDR4
+ injected data register x
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ DR
+ DR
+ regular data register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA
+ Regular data
+ 0
+ 16
+
+
+ ADC2DATA
+ ADC2 data
+ 16
+ 16
+
+
+
+
+
+
+ ADC2
+ Analog to digital converter
+ ADC
+ 0x40012800
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC
+ ADC2 global interrupt
+ 18
+
+
+
+ SR
+ SR
+ status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STRT
+ Regular channel start flag
+ 4
+ 1
+
+
+ JSTRT
+ Injected channel start
+ flag
+ 3
+ 1
+
+
+ JEOC
+ Injected channel end of
+ conversion
+ 2
+ 1
+
+
+ EOC
+ Regular channel end of
+ conversion
+ 1
+ 1
+
+
+ AWD
+ Analog watchdog flag
+ 0
+ 1
+
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDEN
+ Analog watchdog enable on regular
+ channels
+ 23
+ 1
+
+
+ JAWDEN
+ Analog watchdog enable on injected
+ channels
+ 22
+ 1
+
+
+ DISCNUM
+ Discontinuous mode channel
+ count
+ 13
+ 3
+
+
+ JDISCEN
+ Discontinuous mode on injected
+ channels
+ 12
+ 1
+
+
+ DISCEN
+ Discontinuous mode on regular
+ channels
+ 11
+ 1
+
+
+ JAUTO
+ Automatic injected group
+ conversion
+ 10
+ 1
+
+
+ AWDSGL
+ Enable the watchdog on a single channel
+ in scan mode
+ 9
+ 1
+
+
+ SCAN
+ Scan mode
+ 8
+ 1
+
+
+ JEOCIE
+ Interrupt enable for injected
+ channels
+ 7
+ 1
+
+
+ AWDIE
+ Analog watchdog interrupt
+ enable
+ 6
+ 1
+
+
+ EOCIE
+ Interrupt enable for EOC
+ 5
+ 1
+
+
+ AWDCH
+ Analog watchdog channel select
+ bits
+ 0
+ 5
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TSVREFE
+ Temperature sensor and VREFINT
+ enable
+ 23
+ 1
+
+
+ SWSTART
+ Start conversion of regular
+ channels
+ 22
+ 1
+
+
+ JSWSTART
+ Start conversion of injected
+ channels
+ 21
+ 1
+
+
+ EXTTRIG
+ External trigger conversion mode for
+ regular channels
+ 20
+ 1
+
+
+ EXTSEL
+ External event select for regular
+ group
+ 17
+ 3
+
+
+ JEXTTRIG
+ External trigger conversion mode for
+ injected channels
+ 15
+ 1
+
+
+ JEXTSEL
+ External event select for injected
+ group
+ 12
+ 3
+
+
+ ALIGN
+ Data alignment
+ 11
+ 1
+
+
+ DMA
+ Direct memory access mode
+ 8
+ 1
+
+
+ RSTCAL
+ Reset calibration
+ 3
+ 1
+
+
+ CAL
+ A/D calibration
+ 2
+ 1
+
+
+ CONT
+ Continuous conversion
+ 1
+ 1
+
+
+ ADON
+ A/D converter ON / OFF
+ 0
+ 1
+
+
+
+
+ SMPR1
+ SMPR1
+ sample time register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP10
+ Channel 10 sample time
+ selection
+ 0
+ 3
+
+
+ SMP11
+ Channel 11 sample time
+ selection
+ 3
+ 3
+
+
+ SMP12
+ Channel 12 sample time
+ selection
+ 6
+ 3
+
+
+ SMP13
+ Channel 13 sample time
+ selection
+ 9
+ 3
+
+
+ SMP14
+ Channel 14 sample time
+ selection
+ 12
+ 3
+
+
+ SMP15
+ Channel 15 sample time
+ selection
+ 15
+ 3
+
+
+ SMP16
+ Channel 16 sample time
+ selection
+ 18
+ 3
+
+
+ SMP17
+ Channel 17 sample time
+ selection
+ 21
+ 3
+
+
+
+
+ SMPR2
+ SMPR2
+ sample time register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP0
+ Channel 0 sample time
+ selection
+ 0
+ 3
+
+
+ SMP1
+ Channel 1 sample time
+ selection
+ 3
+ 3
+
+
+ SMP2
+ Channel 2 sample time
+ selection
+ 6
+ 3
+
+
+ SMP3
+ Channel 3 sample time
+ selection
+ 9
+ 3
+
+
+ SMP4
+ Channel 4 sample time
+ selection
+ 12
+ 3
+
+
+ SMP5
+ Channel 5 sample time
+ selection
+ 15
+ 3
+
+
+ SMP6
+ Channel 6 sample time
+ selection
+ 18
+ 3
+
+
+ SMP7
+ Channel 7 sample time
+ selection
+ 21
+ 3
+
+
+ SMP8
+ Channel 8 sample time
+ selection
+ 24
+ 3
+
+
+ SMP9
+ Channel 9 sample time
+ selection
+ 27
+ 3
+
+
+
+
+ JOFR1
+ JOFR1
+ injected channel data offset register
+ x
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET1
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR2
+ JOFR2
+ injected channel data offset register
+ x
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET2
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR3
+ JOFR3
+ injected channel data offset register
+ x
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET3
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ JOFR4
+ JOFR4
+ injected channel data offset register
+ x
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JOFFSET4
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ HTR
+ HTR
+ watchdog higher threshold
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ HT
+ Analog watchdog higher
+ threshold
+ 0
+ 12
+
+
+
+
+ LTR
+ LTR
+ watchdog lower threshold
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ SQR1
+ SQR1
+ regular sequence register 1
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ L
+ Regular channel sequence
+ length
+ 20
+ 4
+
+
+ SQ16
+ 16th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ15
+ 15th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ14
+ 14th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ13
+ 13th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ SQR2
+ SQR2
+ regular sequence register 2
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ12
+ 12th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ SQ11
+ 11th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ SQ10
+ 10th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ9
+ 9th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ8
+ 8th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ7
+ 7th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ SQR3
+ SQR3
+ regular sequence register 3
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ6
+ 6th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ SQ5
+ 5th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ SQ4
+ 4th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ SQ3
+ 3rd conversion in regular
+ sequence
+ 10
+ 5
+
+
+ SQ2
+ 2nd conversion in regular
+ sequence
+ 5
+ 5
+
+
+ SQ1
+ 1st conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ JSQR
+ JSQR
+ injected sequence register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ JL
+ Injected sequence length
+ 20
+ 2
+
+
+ JSQ4
+ 4th conversion in injected
+ sequence
+ 15
+ 5
+
+
+ JSQ3
+ 3rd conversion in injected
+ sequence
+ 10
+ 5
+
+
+ JSQ2
+ 2nd conversion in injected
+ sequence
+ 5
+ 5
+
+
+ JSQ1
+ 1st conversion in injected
+ sequence
+ 0
+ 5
+
+
+
+
+ JDR1
+ JDR1
+ injected data register x
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR2
+ JDR2
+ injected data register x
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR3
+ JDR3
+ injected data register x
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ JDR4
+ JDR4
+ injected data register x
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ JDATA
+ Injected data
+ 0
+ 16
+
+
+
+
+ DR
+ DR
+ regular data register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA
+ Regular data
+ 0
+ 16
+
+
+
+
+
+
+ ADC3
+ 0x40013C00
+
+ ADC3
+ ADC3 global interrupt
+ 47
+
+
+
+ CAN
+ Controller area network
+ CAN
+ 0x40006400
+
+ 0x0
+ 0x400
+ registers
+
+
+ CAN1_TX
+ CAN1 TX interrupts
+ 19
+
+
+ CAN1_RX0
+ CAN1 RX0 interrupts
+ 20
+
+
+ CAN1_RX1
+ CAN1 RX1 interrupt
+ 21
+
+
+ CAN1_SCE
+ CAN1 SCE interrupt
+ 22
+
+
+
+ CAN_MCR
+ CAN_MCR
+ CAN_MCR
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBF
+ DBF
+ 16
+ 1
+
+
+ RESET
+ RESET
+ 15
+ 1
+
+
+ TTCM
+ TTCM
+ 7
+ 1
+
+
+ ABOM
+ ABOM
+ 6
+ 1
+
+
+ AWUM
+ AWUM
+ 5
+ 1
+
+
+ NART
+ NART
+ 4
+ 1
+
+
+ RFLM
+ RFLM
+ 3
+ 1
+
+
+ TXFP
+ TXFP
+ 2
+ 1
+
+
+ SLEEP
+ SLEEP
+ 1
+ 1
+
+
+ INRQ
+ INRQ
+ 0
+ 1
+
+
+
+
+ CAN_MSR
+ CAN_MSR
+ CAN_MSR
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ RX
+ RX
+ 11
+ 1
+ read-only
+
+
+ SAMP
+ SAMP
+ 10
+ 1
+ read-only
+
+
+ RXM
+ RXM
+ 9
+ 1
+ read-only
+
+
+ TXM
+ TXM
+ 8
+ 1
+ read-only
+
+
+ SLAKI
+ SLAKI
+ 4
+ 1
+ read-write
+
+
+ WKUI
+ WKUI
+ 3
+ 1
+ read-write
+
+
+ ERRI
+ ERRI
+ 2
+ 1
+ read-write
+
+
+ SLAK
+ SLAK
+ 1
+ 1
+ read-only
+
+
+ INAK
+ INAK
+ 0
+ 1
+ read-only
+
+
+
+
+ CAN_TSR
+ CAN_TSR
+ CAN_TSR
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LOW2
+ Lowest priority flag for mailbox
+ 2
+ 31
+ 1
+ read-only
+
+
+ LOW1
+ Lowest priority flag for mailbox
+ 1
+ 30
+ 1
+ read-only
+
+
+ LOW0
+ Lowest priority flag for mailbox
+ 0
+ 29
+ 1
+ read-only
+
+
+ TME2
+ Lowest priority flag for mailbox
+ 2
+ 28
+ 1
+ read-only
+
+
+ TME1
+ Lowest priority flag for mailbox
+ 1
+ 27
+ 1
+ read-only
+
+
+ TME0
+ Lowest priority flag for mailbox
+ 0
+ 26
+ 1
+ read-only
+
+
+ CODE
+ CODE
+ 24
+ 2
+ read-only
+
+
+ ABRQ2
+ ABRQ2
+ 23
+ 1
+ read-write
+
+
+ TERR2
+ TERR2
+ 19
+ 1
+ read-write
+
+
+ ALST2
+ ALST2
+ 18
+ 1
+ read-write
+
+
+ TXOK2
+ TXOK2
+ 17
+ 1
+ read-write
+
+
+ RQCP2
+ RQCP2
+ 16
+ 1
+ read-write
+
+
+ ABRQ1
+ ABRQ1
+ 15
+ 1
+ read-write
+
+
+ TERR1
+ TERR1
+ 11
+ 1
+ read-write
+
+
+ ALST1
+ ALST1
+ 10
+ 1
+ read-write
+
+
+ TXOK1
+ TXOK1
+ 9
+ 1
+ read-write
+
+
+ RQCP1
+ RQCP1
+ 8
+ 1
+ read-write
+
+
+ ABRQ0
+ ABRQ0
+ 7
+ 1
+ read-write
+
+
+ TERR0
+ TERR0
+ 3
+ 1
+ read-write
+
+
+ ALST0
+ ALST0
+ 2
+ 1
+ read-write
+
+
+ TXOK0
+ TXOK0
+ 1
+ 1
+ read-write
+
+
+ RQCP0
+ RQCP0
+ 0
+ 1
+ read-write
+
+
+
+
+ CAN_RF0R
+ CAN_RF0R
+ CAN_RF0R
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ RFOM0
+ RFOM0
+ 5
+ 1
+ read-write
+
+
+ FOVR0
+ FOVR0
+ 4
+ 1
+ read-write
+
+
+ FULL0
+ FULL0
+ 3
+ 1
+ read-write
+
+
+ FMP0
+ FMP0
+ 0
+ 2
+ read-only
+
+
+
+
+ CAN_RF1R
+ CAN_RF1R
+ CAN_RF1R
+ 0x10
+ 0x20
+ 0x00000000
+
+
+ RFOM1
+ RFOM1
+ 5
+ 1
+ read-write
+
+
+ FOVR1
+ FOVR1
+ 4
+ 1
+ read-write
+
+
+ FULL1
+ FULL1
+ 3
+ 1
+ read-write
+
+
+ FMP1
+ FMP1
+ 0
+ 2
+ read-only
+
+
+
+
+ CAN_IER
+ CAN_IER
+ CAN_IER
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLKIE
+ SLKIE
+ 17
+ 1
+
+
+ WKUIE
+ WKUIE
+ 16
+ 1
+
+
+ ERRIE
+ ERRIE
+ 15
+ 1
+
+
+ LECIE
+ LECIE
+ 11
+ 1
+
+
+ BOFIE
+ BOFIE
+ 10
+ 1
+
+
+ EPVIE
+ EPVIE
+ 9
+ 1
+
+
+ EWGIE
+ EWGIE
+ 8
+ 1
+
+
+ FOVIE1
+ FOVIE1
+ 6
+ 1
+
+
+ FFIE1
+ FFIE1
+ 5
+ 1
+
+
+ FMPIE1
+ FMPIE1
+ 4
+ 1
+
+
+ FOVIE0
+ FOVIE0
+ 3
+ 1
+
+
+ FFIE0
+ FFIE0
+ 2
+ 1
+
+
+ FMPIE0
+ FMPIE0
+ 1
+ 1
+
+
+ TMEIE
+ TMEIE
+ 0
+ 1
+
+
+
+
+ CAN_ESR
+ CAN_ESR
+ CAN_ESR
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ REC
+ REC
+ 24
+ 8
+ read-only
+
+
+ TEC
+ TEC
+ 16
+ 8
+ read-only
+
+
+ LEC
+ LEC
+ 4
+ 3
+ read-write
+
+
+ BOFF
+ BOFF
+ 2
+ 1
+ read-only
+
+
+ EPVF
+ EPVF
+ 1
+ 1
+ read-only
+
+
+ EWGF
+ EWGF
+ 0
+ 1
+ read-only
+
+
+
+
+ CAN_BTR
+ CAN_BTR
+ CAN_BTR
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SILM
+ SILM
+ 31
+ 1
+
+
+ LBKM
+ LBKM
+ 30
+ 1
+
+
+ SJW
+ SJW
+ 24
+ 2
+
+
+ TS2
+ TS2
+ 20
+ 3
+
+
+ TS1
+ TS1
+ 16
+ 4
+
+
+ BRP
+ BRP
+ 0
+ 10
+
+
+
+
+ CAN_TI0R
+ CAN_TI0R
+ CAN_TI0R
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ CAN_TDT0R
+ CAN_TDT0R
+ CAN_TDT0R
+ 0x184
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ CAN_TDL0R
+ CAN_TDL0R
+ CAN_TDL0R
+ 0x188
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ CAN_TDH0R
+ CAN_TDH0R
+ CAN_TDH0R
+ 0x18C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ CAN_TI1R
+ CAN_TI1R
+ CAN_TI1R
+ 0x190
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ CAN_TDT1R
+ CAN_TDT1R
+ CAN_TDT1R
+ 0x194
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ CAN_TDL1R
+ CAN_TDL1R
+ CAN_TDL1R
+ 0x198
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ CAN_TDH1R
+ CAN_TDH1R
+ CAN_TDH1R
+ 0x19C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ CAN_TI2R
+ CAN_TI2R
+ CAN_TI2R
+ 0x1A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+ TXRQ
+ TXRQ
+ 0
+ 1
+
+
+
+
+ CAN_TDT2R
+ CAN_TDT2R
+ CAN_TDT2R
+ 0x1A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ TGT
+ TGT
+ 8
+ 1
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ CAN_TDL2R
+ CAN_TDL2R
+ CAN_TDL2R
+ 0x1A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ CAN_TDH2R
+ CAN_TDH2R
+ CAN_TDH2R
+ 0x1AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ CAN_RI0R
+ CAN_RI0R
+ CAN_RI0R
+ 0x1B0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+
+
+ CAN_RDT0R
+ CAN_RDT0R
+ CAN_RDT0R
+ 0x1B4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ FMI
+ FMI
+ 8
+ 8
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ CAN_RDL0R
+ CAN_RDL0R
+ CAN_RDL0R
+ 0x1B8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ CAN_RDH0R
+ CAN_RDH0R
+ CAN_RDH0R
+ 0x1BC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ CAN_RI1R
+ CAN_RI1R
+ CAN_RI1R
+ 0x1C0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ STID
+ STID
+ 21
+ 11
+
+
+ EXID
+ EXID
+ 3
+ 18
+
+
+ IDE
+ IDE
+ 2
+ 1
+
+
+ RTR
+ RTR
+ 1
+ 1
+
+
+
+
+ CAN_RDT1R
+ CAN_RDT1R
+ CAN_RDT1R
+ 0x1C4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TIME
+ TIME
+ 16
+ 16
+
+
+ FMI
+ FMI
+ 8
+ 8
+
+
+ DLC
+ DLC
+ 0
+ 4
+
+
+
+
+ CAN_RDL1R
+ CAN_RDL1R
+ CAN_RDL1R
+ 0x1C8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA3
+ DATA3
+ 24
+ 8
+
+
+ DATA2
+ DATA2
+ 16
+ 8
+
+
+ DATA1
+ DATA1
+ 8
+ 8
+
+
+ DATA0
+ DATA0
+ 0
+ 8
+
+
+
+
+ CAN_RDH1R
+ CAN_RDH1R
+ CAN_RDH1R
+ 0x1CC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DATA7
+ DATA7
+ 24
+ 8
+
+
+ DATA6
+ DATA6
+ 16
+ 8
+
+
+ DATA5
+ DATA5
+ 8
+ 8
+
+
+ DATA4
+ DATA4
+ 0
+ 8
+
+
+
+
+ CAN_FMR
+ CAN_FMR
+ CAN_FMR
+ 0x200
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FINIT
+ FINIT
+ 0
+ 1
+
+
+
+
+ CAN_FM1R
+ CAN_FM1R
+ CAN_FM1R
+ 0x204
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FBM0
+ Filter mode
+ 0
+ 1
+
+
+ FBM1
+ Filter mode
+ 1
+ 1
+
+
+ FBM2
+ Filter mode
+ 2
+ 1
+
+
+ FBM3
+ Filter mode
+ 3
+ 1
+
+
+ FBM4
+ Filter mode
+ 4
+ 1
+
+
+ FBM5
+ Filter mode
+ 5
+ 1
+
+
+ FBM6
+ Filter mode
+ 6
+ 1
+
+
+ FBM7
+ Filter mode
+ 7
+ 1
+
+
+ FBM8
+ Filter mode
+ 8
+ 1
+
+
+ FBM9
+ Filter mode
+ 9
+ 1
+
+
+ FBM10
+ Filter mode
+ 10
+ 1
+
+
+ FBM11
+ Filter mode
+ 11
+ 1
+
+
+ FBM12
+ Filter mode
+ 12
+ 1
+
+
+ FBM13
+ Filter mode
+ 13
+ 1
+
+
+
+
+ CAN_FS1R
+ CAN_FS1R
+ CAN_FS1R
+ 0x20C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FSC0
+ Filter scale configuration
+ 0
+ 1
+
+
+ FSC1
+ Filter scale configuration
+ 1
+ 1
+
+
+ FSC2
+ Filter scale configuration
+ 2
+ 1
+
+
+ FSC3
+ Filter scale configuration
+ 3
+ 1
+
+
+ FSC4
+ Filter scale configuration
+ 4
+ 1
+
+
+ FSC5
+ Filter scale configuration
+ 5
+ 1
+
+
+ FSC6
+ Filter scale configuration
+ 6
+ 1
+
+
+ FSC7
+ Filter scale configuration
+ 7
+ 1
+
+
+ FSC8
+ Filter scale configuration
+ 8
+ 1
+
+
+ FSC9
+ Filter scale configuration
+ 9
+ 1
+
+
+ FSC10
+ Filter scale configuration
+ 10
+ 1
+
+
+ FSC11
+ Filter scale configuration
+ 11
+ 1
+
+
+ FSC12
+ Filter scale configuration
+ 12
+ 1
+
+
+ FSC13
+ Filter scale configuration
+ 13
+ 1
+
+
+
+
+ CAN_FFA1R
+ CAN_FFA1R
+ CAN_FFA1R
+ 0x214
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FFA0
+ Filter FIFO assignment for filter
+ 0
+ 0
+ 1
+
+
+ FFA1
+ Filter FIFO assignment for filter
+ 1
+ 1
+ 1
+
+
+ FFA2
+ Filter FIFO assignment for filter
+ 2
+ 2
+ 1
+
+
+ FFA3
+ Filter FIFO assignment for filter
+ 3
+ 3
+ 1
+
+
+ FFA4
+ Filter FIFO assignment for filter
+ 4
+ 4
+ 1
+
+
+ FFA5
+ Filter FIFO assignment for filter
+ 5
+ 5
+ 1
+
+
+ FFA6
+ Filter FIFO assignment for filter
+ 6
+ 6
+ 1
+
+
+ FFA7
+ Filter FIFO assignment for filter
+ 7
+ 7
+ 1
+
+
+ FFA8
+ Filter FIFO assignment for filter
+ 8
+ 8
+ 1
+
+
+ FFA9
+ Filter FIFO assignment for filter
+ 9
+ 9
+ 1
+
+
+ FFA10
+ Filter FIFO assignment for filter
+ 10
+ 10
+ 1
+
+
+ FFA11
+ Filter FIFO assignment for filter
+ 11
+ 11
+ 1
+
+
+ FFA12
+ Filter FIFO assignment for filter
+ 12
+ 12
+ 1
+
+
+ FFA13
+ Filter FIFO assignment for filter
+ 13
+ 13
+ 1
+
+
+
+
+ CAN_FA1R
+ CAN_FA1R
+ CAN_FA1R
+ 0x21C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FACT0
+ Filter active
+ 0
+ 1
+
+
+ FACT1
+ Filter active
+ 1
+ 1
+
+
+ FACT2
+ Filter active
+ 2
+ 1
+
+
+ FACT3
+ Filter active
+ 3
+ 1
+
+
+ FACT4
+ Filter active
+ 4
+ 1
+
+
+ FACT5
+ Filter active
+ 5
+ 1
+
+
+ FACT6
+ Filter active
+ 6
+ 1
+
+
+ FACT7
+ Filter active
+ 7
+ 1
+
+
+ FACT8
+ Filter active
+ 8
+ 1
+
+
+ FACT9
+ Filter active
+ 9
+ 1
+
+
+ FACT10
+ Filter active
+ 10
+ 1
+
+
+ FACT11
+ Filter active
+ 11
+ 1
+
+
+ FACT12
+ Filter active
+ 12
+ 1
+
+
+ FACT13
+ Filter active
+ 13
+ 1
+
+
+
+
+ F0R1
+ F0R1
+ Filter bank 0 register 1
+ 0x240
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F0R2
+ F0R2
+ Filter bank 0 register 2
+ 0x244
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F1R1
+ F1R1
+ Filter bank 1 register 1
+ 0x248
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F1R2
+ F1R2
+ Filter bank 1 register 2
+ 0x24C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F2R1
+ F2R1
+ Filter bank 2 register 1
+ 0x250
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F2R2
+ F2R2
+ Filter bank 2 register 2
+ 0x254
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F3R1
+ F3R1
+ Filter bank 3 register 1
+ 0x258
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F3R2
+ F3R2
+ Filter bank 3 register 2
+ 0x25C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F4R1
+ F4R1
+ Filter bank 4 register 1
+ 0x260
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F4R2
+ F4R2
+ Filter bank 4 register 2
+ 0x264
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F5R1
+ F5R1
+ Filter bank 5 register 1
+ 0x268
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F5R2
+ F5R2
+ Filter bank 5 register 2
+ 0x26C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F6R1
+ F6R1
+ Filter bank 6 register 1
+ 0x270
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F6R2
+ F6R2
+ Filter bank 6 register 2
+ 0x274
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+
+ F7R1
+ F7R1
+ Filter bank 7 register 1
+ 0x278
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F7R2
+ F7R2
+ Filter bank 7 register 2
+ 0x27C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F8R1
+ F8R1
+ Filter bank 8 register 1
+ 0x280
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F8R2
+ F8R2
+ Filter bank 8 register 2
+ 0x284
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F9R1
+ F9R1
+ Filter bank 9 register 1
+ 0x288
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F9R2
+ F9R2
+ Filter bank 9 register 2
+ 0x28C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F10R1
+ F10R1
+ Filter bank 10 register 1
+ 0x290
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F10R2
+ F10R2
+ Filter bank 10 register 2
+ 0x294
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F11R1
+ F11R1
+ Filter bank 11 register 1
+ 0x298
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F11R2
+ F11R2
+ Filter bank 11 register 2
+ 0x29C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F12R1
+ F12R1
+ Filter bank 4 register 1
+ 0x2A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F12R2
+ F12R2
+ Filter bank 12 register 2
+ 0x2A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F13R1
+ F13R1
+ Filter bank 13 register 1
+ 0x2A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+ F13R2
+ F13R2
+ Filter bank 13 register 2
+ 0x2AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FB0
+ Filter bits
+ 0
+ 1
+
+
+ FB1
+ Filter bits
+ 1
+ 1
+
+
+ FB2
+ Filter bits
+ 2
+ 1
+
+
+ FB3
+ Filter bits
+ 3
+ 1
+
+
+ FB4
+ Filter bits
+ 4
+ 1
+
+
+ FB5
+ Filter bits
+ 5
+ 1
+
+
+ FB6
+ Filter bits
+ 6
+ 1
+
+
+ FB7
+ Filter bits
+ 7
+ 1
+
+
+ FB8
+ Filter bits
+ 8
+ 1
+
+
+ FB9
+ Filter bits
+ 9
+ 1
+
+
+ FB10
+ Filter bits
+ 10
+ 1
+
+
+ FB11
+ Filter bits
+ 11
+ 1
+
+
+ FB12
+ Filter bits
+ 12
+ 1
+
+
+ FB13
+ Filter bits
+ 13
+ 1
+
+
+ FB14
+ Filter bits
+ 14
+ 1
+
+
+ FB15
+ Filter bits
+ 15
+ 1
+
+
+ FB16
+ Filter bits
+ 16
+ 1
+
+
+ FB17
+ Filter bits
+ 17
+ 1
+
+
+ FB18
+ Filter bits
+ 18
+ 1
+
+
+ FB19
+ Filter bits
+ 19
+ 1
+
+
+ FB20
+ Filter bits
+ 20
+ 1
+
+
+ FB21
+ Filter bits
+ 21
+ 1
+
+
+ FB22
+ Filter bits
+ 22
+ 1
+
+
+ FB23
+ Filter bits
+ 23
+ 1
+
+
+ FB24
+ Filter bits
+ 24
+ 1
+
+
+ FB25
+ Filter bits
+ 25
+ 1
+
+
+ FB26
+ Filter bits
+ 26
+ 1
+
+
+ FB27
+ Filter bits
+ 27
+ 1
+
+
+ FB28
+ Filter bits
+ 28
+ 1
+
+
+ FB29
+ Filter bits
+ 29
+ 1
+
+
+ FB30
+ Filter bits
+ 30
+ 1
+
+
+ FB31
+ Filter bits
+ 31
+ 1
+
+
+
+
+
+
+ DAC
+ Digital to analog converter
+ DAC
+ 0x40007400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR
+ CR
+ Control register (DAC_CR)
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN1
+ DAC channel1 enable
+ 0
+ 1
+
+
+ BOFF1
+ DAC channel1 output buffer
+ disable
+ 1
+ 1
+
+
+ TEN1
+ DAC channel1 trigger
+ enable
+ 2
+ 1
+
+
+ TSEL1
+ DAC channel1 trigger
+ selection
+ 3
+ 3
+
+
+ WAVE1
+ DAC channel1 noise/triangle wave
+ generation enable
+ 6
+ 2
+
+
+ MAMP1
+ DAC channel1 mask/amplitude
+ selector
+ 8
+ 4
+
+
+ DMAEN1
+ DAC channel1 DMA enable
+ 12
+ 1
+
+
+ EN2
+ DAC channel2 enable
+ 16
+ 1
+
+
+ BOFF2
+ DAC channel2 output buffer
+ disable
+ 17
+ 1
+
+
+ TEN2
+ DAC channel2 trigger
+ enable
+ 18
+ 1
+
+
+ TSEL2
+ DAC channel2 trigger
+ selection
+ 19
+ 3
+
+
+ WAVE2
+ DAC channel2 noise/triangle wave
+ generation enable
+ 22
+ 2
+
+
+ MAMP2
+ DAC channel2 mask/amplitude
+ selector
+ 24
+ 4
+
+
+ DMAEN2
+ DAC channel2 DMA enable
+ 28
+ 1
+
+
+
+
+ SWTRIGR
+ SWTRIGR
+ DAC software trigger register
+ (DAC_SWTRIGR)
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SWTRIG1
+ DAC channel1 software
+ trigger
+ 0
+ 1
+
+
+ SWTRIG2
+ DAC channel2 software
+ trigger
+ 1
+ 1
+
+
+
+
+ DHR12R1
+ DHR12R1
+ DAC channel1 12-bit right-aligned data
+ holding register(DAC_DHR12R1)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L1
+ DHR12L1
+ DAC channel1 12-bit left aligned data
+ holding register (DAC_DHR12L1)
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R1
+ DHR8R1
+ DAC channel1 8-bit right aligned data
+ holding register (DAC_DHR8R1)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12R2
+ DHR12R2
+ DAC channel2 12-bit right aligned data
+ holding register (DAC_DHR12R2)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+
+
+ DHR12L2
+ DHR12L2
+ DAC channel2 12-bit left aligned data
+ holding register (DAC_DHR12L2)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+
+
+ DHR8R2
+ DHR8R2
+ DAC channel2 8-bit right-aligned data
+ holding register (DAC_DHR8R2)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+
+
+ DHR12RD
+ DHR12RD
+ Dual DAC 12-bit right-aligned data holding
+ register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12
+ Reserved
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit right-aligned
+ data
+ 0
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 16
+ 12
+
+
+
+
+ DHR12LD
+ DHR12LD
+ DUAL DAC 12-bit left aligned data holding
+ register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0
+ Reserved
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 12-bit left-aligned
+ data
+ 4
+ 12
+
+
+ DACC2DHR
+ DAC channel2 12-bit right-aligned
+ data
+ 20
+ 12
+
+
+
+
+ DHR8RD
+ DHR8RD
+ DUAL DAC 8-bit right aligned data holding
+ register (DAC_DHR8RD), Bits 31:16 Reserved
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DACC1DHR
+ DAC channel1 8-bit right-aligned
+ data
+ 0
+ 8
+
+
+ DACC2DHR
+ DAC channel2 8-bit right-aligned
+ data
+ 8
+ 8
+
+
+
+
+ DOR1
+ DOR1
+ DAC channel1 data output register
+ (DAC_DOR1)
+ 0x2C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC1DOR
+ DAC channel1 data output
+ 0
+ 12
+
+
+
+
+ DOR2
+ DOR2
+ DAC channel2 data output register
+ (DAC_DOR2)
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DACC2DOR
+ DAC channel2 data output
+ 0
+ 12
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBG
+ 0xE0042000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ IDCODE
+ IDCODE
+ DBGMCU_IDCODE
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ DEV_ID
+ 0
+ 12
+
+
+ REV_ID
+ REV_ID
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ DBGMCU_CR
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_SLEEP
+ DBG_SLEEP
+ 0
+ 1
+
+
+ DBG_STOP
+ DBG_STOP
+ 1
+ 1
+
+
+ DBG_STANDBY
+ DBG_STANDBY
+ 2
+ 1
+
+
+ TRACE_IOEN
+ TRACE_IOEN
+ 5
+ 1
+
+
+ TRACE_MODE
+ TRACE_MODE
+ 6
+ 2
+
+
+ DBG_IWDG_STOP
+ DBG_IWDG_STOP
+ 8
+ 1
+
+
+ DBG_WWDG_STOP
+ DBG_WWDG_STOP
+ 9
+ 1
+
+
+ DBG_TIM1_STOP
+ DBG_TIM1_STOP
+ 10
+ 1
+
+
+ DBG_TIM2_STOP
+ DBG_TIM2_STOP
+ 11
+ 1
+
+
+ DBG_TIM3_STOP
+ DBG_TIM3_STOP
+ 12
+ 1
+
+
+ DBG_TIM4_STOP
+ DBG_TIM4_STOP
+ 13
+ 1
+
+
+ DBG_CAN1_STOP
+ DBG_CAN1_STOP
+ 14
+ 1
+
+
+ DBG_I2C1_SMBUS_TIMEOUT
+ DBG_I2C1_SMBUS_TIMEOUT
+ 15
+ 1
+
+
+ DBG_I2C2_SMBUS_TIMEOUT
+ DBG_I2C2_SMBUS_TIMEOUT
+ 16
+ 1
+
+
+ DBG_TIM8_STOP
+ DBG_TIM8_STOP
+ 17
+ 1
+
+
+ DBG_TIM5_STOP
+ DBG_TIM5_STOP
+ 18
+ 1
+
+
+ DBG_TIM6_STOP
+ DBG_TIM6_STOP
+ 19
+ 1
+
+
+ DBG_TIM7_STOP
+ DBG_TIM7_STOP
+ 20
+ 1
+
+
+ DBG_CAN2_STOP
+ DBG_CAN2_STOP
+ 21
+ 1
+
+
+
+
+
+
+ UART4
+ Universal asynchronous receiver
+ transmitter
+ USART
+ 0x40004C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ UART4
+ UART4 global interrupt
+ 52
+
+
+
+ SR
+ SR
+ UART4_SR
+ 0x0
+ 0x20
+ 0x0
+
+
+ PE
+ Parity error
+ 0
+ 1
+ read-only
+
+
+ FE
+ Framing error
+ 1
+ 1
+ read-only
+
+
+ NE
+ Noise error flag
+ 2
+ 1
+ read-only
+
+
+ ORE
+ Overrun error
+ 3
+ 1
+ read-only
+
+
+ IDLE
+ IDLE line detected
+ 4
+ 1
+ read-only
+
+
+ RXNE
+ Read data register not
+ empty
+ 5
+ 1
+ read-write
+
+
+ TC
+ Transmission complete
+ 6
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register
+ empty
+ 7
+ 1
+ read-only
+
+
+ LBD
+ LIN break detection flag
+ 8
+ 1
+ read-write
+
+
+
+
+ DR
+ DR
+ UART4_DR
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DR
+ DR
+ 0
+ 9
+
+
+
+
+ BRR
+ BRR
+ UART4_BRR
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DIV_Fraction
+ DIV_Fraction
+ 0
+ 4
+
+
+ DIV_Mantissa
+ DIV_Mantissa
+ 4
+ 12
+
+
+
+
+ CR1
+ CR1
+ UART4_CR1
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ SBK
+ Send break
+ 0
+ 1
+
+
+ RWU
+ Receiver wakeup
+ 1
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ TXE interrupt enable
+ 7
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ WAKE
+ Wakeup method
+ 11
+ 1
+
+
+ M
+ Word length
+ 12
+ 1
+
+
+ UE
+ USART enable
+ 13
+ 1
+
+
+
+
+ CR2
+ CR2
+ UART4_CR2
+ 0x10
+ 0x20
+ read-write
+ 0x0
+
+
+ ADD
+ Address of the USART node
+ 0
+ 4
+
+
+ LBDL
+ lin break detection length
+ 5
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+
+
+ CR3
+ CR3
+ UART4_CR3
+ 0x14
+ 0x20
+ read-write
+ 0x0
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+
+
+
+
+ UART5
+ Universal asynchronous receiver
+ transmitter
+ USART
+ 0x40005000
+
+ 0x0
+ 0x400
+ registers
+
+
+ UART5
+ UART5 global interrupt
+ 53
+
+
+
+ SR
+ SR
+ UART4_SR
+ 0x0
+ 0x20
+ 0x0
+
+
+ PE
+ PE
+ 0
+ 1
+ read-only
+
+
+ FE
+ FE
+ 1
+ 1
+ read-only
+
+
+ NE
+ NE
+ 2
+ 1
+ read-only
+
+
+ ORE
+ ORE
+ 3
+ 1
+ read-only
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+ read-only
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+ read-write
+
+
+ TC
+ TC
+ 6
+ 1
+ read-write
+
+
+ TXE
+ TXE
+ 7
+ 1
+ read-only
+
+
+ LBD
+ LBD
+ 8
+ 1
+ read-write
+
+
+
+
+ DR
+ DR
+ UART4_DR
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DR
+ DR
+ 0
+ 9
+
+
+
+
+ BRR
+ BRR
+ UART4_BRR
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DIV_Fraction
+ DIV_Fraction
+ 0
+ 4
+
+
+ DIV_Mantissa
+ DIV_Mantissa
+ 4
+ 12
+
+
+
+
+ CR1
+ CR1
+ UART4_CR1
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ SBK
+ SBK
+ 0
+ 1
+
+
+ RWU
+ RWU
+ 1
+ 1
+
+
+ RE
+ RE
+ 2
+ 1
+
+
+ TE
+ TE
+ 3
+ 1
+
+
+ IDLEIE
+ IDLEIE
+ 4
+ 1
+
+
+ RXNEIE
+ RXNEIE
+ 5
+ 1
+
+
+ TCIE
+ TCIE
+ 6
+ 1
+
+
+ TXEIE
+ TXEIE
+ 7
+ 1
+
+
+ PEIE
+ PEIE
+ 8
+ 1
+
+
+ PS
+ PS
+ 9
+ 1
+
+
+ PCE
+ PCE
+ 10
+ 1
+
+
+ WAKE
+ WAKE
+ 11
+ 1
+
+
+ M
+ M
+ 12
+ 1
+
+
+ UE
+ UE
+ 13
+ 1
+
+
+
+
+ CR2
+ CR2
+ UART4_CR2
+ 0x10
+ 0x20
+ read-write
+ 0x0
+
+
+ ADD
+ ADD
+ 0
+ 4
+
+
+ LBDL
+ LBDL
+ 5
+ 1
+
+
+ LBDIE
+ LBDIE
+ 6
+ 1
+
+
+ STOP
+ STOP
+ 12
+ 2
+
+
+ LINEN
+ LINEN
+ 14
+ 1
+
+
+
+
+ CR3
+ CR3
+ UART4_CR3
+ 0x14
+ 0x20
+ read-write
+ 0x0
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+
+
+
+
+ CRC
+ CRC calculation unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data Register
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent Data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ Independent Data register
+ 0
+ 8
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ RESET
+ Reset bit
+ 0
+ 1
+
+
+
+
+
+
+ FLASH
+ FLASH
+ FLASH
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 4
+
+
+
+ ACR
+ ACR
+ Flash access control register
+ 0x0
+ 0x20
+ 0x00000030
+
+
+ LATENCY
+ Latency
+ 0
+ 3
+ read-write
+
+
+ HLFCYA
+ Flash half cycle access
+ enable
+ 3
+ 1
+ read-write
+
+
+ PRFTBE
+ Prefetch buffer enable
+ 4
+ 1
+ read-write
+
+
+ PRFTBS
+ Prefetch buffer status
+ 5
+ 1
+ read-only
+
+
+
+
+ KEYR
+ KEYR
+ Flash key register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ FPEC key
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Flash option key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEY
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ EOP
+ End of operation
+ 5
+ 1
+ read-write
+
+
+ WRPRTERR
+ Write protection error
+ 4
+ 1
+ read-write
+
+
+ PGERR
+ Programming error
+ 2
+ 1
+ read-write
+
+
+ BSY
+ Busy
+ 0
+ 1
+ read-only
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ PG
+ Programming
+ 0
+ 1
+
+
+ PER
+ Page Erase
+ 1
+ 1
+
+
+ MER
+ Mass Erase
+ 2
+ 1
+
+
+ OPTPG
+ Option byte programming
+ 4
+ 1
+
+
+ OPTER
+ Option byte erase
+ 5
+ 1
+
+
+ STRT
+ Start
+ 6
+ 1
+
+
+ LOCK
+ Lock
+ 7
+ 1
+
+
+ OPTWRE
+ Option bytes write enable
+ 9
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ EOPIE
+ End of operation interrupt
+ enable
+ 12
+ 1
+
+
+
+
+ AR
+ AR
+ Flash address register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ FAR
+ Flash Address
+ 0
+ 32
+
+
+
+
+ OBR
+ OBR
+ Option byte register
+ 0x1C
+ 0x20
+ read-only
+ 0x03FFFFFC
+
+
+ OPTERR
+ Option byte error
+ 0
+ 1
+
+
+ RDPRT
+ Read protection
+ 1
+ 1
+
+
+ WDG_SW
+ WDG_SW
+ 2
+ 1
+
+
+ nRST_STOP
+ nRST_STOP
+ 3
+ 1
+
+
+ nRST_STDBY
+ nRST_STDBY
+ 4
+ 1
+
+
+ Data0
+ Data0
+ 10
+ 8
+
+
+ Data1
+ Data1
+ 18
+ 8
+
+
+
+
+ WRPR
+ WRPR
+ Write protection register
+ 0x20
+ 0x20
+ read-only
+ 0xFFFFFFFF
+
+
+ WRP
+ Write protect
+ 0
+ 32
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E000
+
+ 0x0
+ 0x1001
+ registers
+
+
+
+ ICTR
+ ICTR
+ Interrupt Controller Type
+ Register
+ 0x4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ INTLINESNUM
+ Total number of interrupt lines in
+ groups
+ 0
+ 4
+
+
+
+
+ STIR
+ STIR
+ Software Triggered Interrupt
+ Register
+ 0xF00
+ 0x20
+ write-only
+ 0x00000000
+
+
+ INTID
+ interrupt to be triggered
+ 0
+ 9
+
+
+
+
+ ISER0
+ ISER0
+ Interrupt Set-Enable Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER1
+ ISER1
+ Interrupt Set-Enable Register
+ 0x104
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER0
+ ICER0
+ Interrupt Clear-Enable
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER1
+ ICER1
+ Interrupt Clear-Enable
+ Register
+ 0x184
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR0
+ ISPR0
+ Interrupt Set-Pending Register
+ 0x200
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR1
+ ISPR1
+ Interrupt Set-Pending Register
+ 0x204
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR0
+ ICPR0
+ Interrupt Clear-Pending
+ Register
+ 0x280
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR1
+ ICPR1
+ Interrupt Clear-Pending
+ Register
+ 0x284
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IABR0
+ IABR0
+ Interrupt Active Bit Register
+ 0x300
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ACTIVE
+ ACTIVE
+ 0
+ 32
+
+
+
+
+ IABR1
+ IABR1
+ Interrupt Active Bit Register
+ 0x304
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ACTIVE
+ ACTIVE
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register
+ 0x400
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register
+ 0x404
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register
+ 0x408
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register
+ 0x40C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register
+ 0x410
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register
+ 0x414
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register
+ 0x418
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register
+ 0x41C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR8
+ IPR8
+ Interrupt Priority Register
+ 0x420
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR9
+ IPR9
+ Interrupt Priority Register
+ 0x424
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR10
+ IPR10
+ Interrupt Priority Register
+ 0x428
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR11
+ IPR11
+ Interrupt Priority Register
+ 0x42C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR12
+ IPR12
+ Interrupt Priority Register
+ 0x430
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR13
+ IPR13
+ Interrupt Priority Register
+ 0x434
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+ IPR14
+ IPR14
+ Interrupt Priority Register
+ 0x438
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IPR_N0
+ IPR_N0
+ 0
+ 8
+
+
+ IPR_N1
+ IPR_N1
+ 8
+ 8
+
+
+ IPR_N2
+ IPR_N2
+ 16
+ 8
+
+
+ IPR_N3
+ IPR_N3
+ 24
+ 8
+
+
+
+
+
+
+ USB
+ Universal serial bus full-speed device
+ interface
+ USB
+ 0x40005C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ USB_FS_WKUP
+ USB Device FS Wakeup through EXTI line
+ interrupt
+ 42
+
+
+
+ EP0R
+ EP0R
+ endpoint 0 register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP1R
+ EP1R
+ endpoint 1 register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP2R
+ EP2R
+ endpoint 2 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP3R
+ EP3R
+ endpoint 3 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP4R
+ EP4R
+ endpoint 4 register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP5R
+ EP5R
+ endpoint 5 register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP6R
+ EP6R
+ endpoint 6 register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ EP7R
+ EP7R
+ endpoint 7 register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EA
+ Endpoint address
+ 0
+ 4
+
+
+ STAT_TX
+ Status bits, for transmission
+ transfers
+ 4
+ 2
+
+
+ DTOG_TX
+ Data Toggle, for transmission
+ transfers
+ 6
+ 1
+
+
+ CTR_TX
+ Correct Transfer for
+ transmission
+ 7
+ 1
+
+
+ EP_KIND
+ Endpoint kind
+ 8
+ 1
+
+
+ EP_TYPE
+ Endpoint type
+ 9
+ 2
+
+
+ SETUP
+ Setup transaction
+ completed
+ 11
+ 1
+
+
+ STAT_RX
+ Status bits, for reception
+ transfers
+ 12
+ 2
+
+
+ DTOG_RX
+ Data Toggle, for reception
+ transfers
+ 14
+ 1
+
+
+ CTR_RX
+ Correct transfer for
+ reception
+ 15
+ 1
+
+
+
+
+ CNTR
+ USB_CNTR
+ control register
+ 0x40
+ 0x20
+ read-write
+ 0x00000003
+
+
+ FRES
+ Force USB Reset
+ 0
+ 1
+
+
+ PDWN
+ Power down
+ 1
+ 1
+
+
+ LPMODE
+ Low-power mode
+ 2
+ 1
+
+
+ FSUSP
+ Force suspend
+ 3
+ 1
+
+
+ RESUME
+ Resume request
+ 4
+ 1
+
+
+ ESOFM
+ Expected start of frame interrupt
+ mask
+ 8
+ 1
+
+
+ SOFM
+ Start of frame interrupt
+ mask
+ 9
+ 1
+
+
+ RESETM
+ USB reset interrupt mask
+ 10
+ 1
+
+
+ SUSPM
+ Suspend mode interrupt
+ mask
+ 11
+ 1
+
+
+ WKUPM
+ Wakeup interrupt mask
+ 12
+ 1
+
+
+ ERRM
+ Error interrupt mask
+ 13
+ 1
+
+
+ PMAOVRM
+ Packet memory area over / underrun
+ interrupt mask
+ 14
+ 1
+
+
+ CTRM
+ Correct transfer interrupt
+ mask
+ 15
+ 1
+
+
+
+
+ ISTR
+ ISTR
+ interrupt status register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EP_ID
+ Endpoint Identifier
+ 0
+ 4
+
+
+ DIR
+ Direction of transaction
+ 4
+ 1
+
+
+ ESOF
+ Expected start frame
+ 8
+ 1
+
+
+ SOF
+ start of frame
+ 9
+ 1
+
+
+ RESET
+ reset request
+ 10
+ 1
+
+
+ SUSP
+ Suspend mode request
+ 11
+ 1
+
+
+ WKUP
+ Wakeup
+ 12
+ 1
+
+
+ ERR
+ Error
+ 13
+ 1
+
+
+ PMAOVR
+ Packet memory area over /
+ underrun
+ 14
+ 1
+
+
+ CTR
+ Correct transfer
+ 15
+ 1
+
+
+
+
+ FNR
+ FNR
+ frame number register
+ 0x48
+ 0x20
+ read-only
+ 0x0000
+
+
+ FN
+ Frame number
+ 0
+ 11
+
+
+ LSOF
+ Lost SOF
+ 11
+ 2
+
+
+ LCK
+ Locked
+ 13
+ 1
+
+
+ RXDM
+ Receive data - line status
+ 14
+ 1
+
+
+ RXDP
+ Receive data + line status
+ 15
+ 1
+
+
+
+
+ DADDR
+ DADDR
+ device address
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD
+ Device address
+ 0
+ 7
+
+
+ EF
+ Enable function
+ 7
+ 1
+
+
+
+
+ BTABLE
+ BTABLE
+ Buffer table address
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTABLE
+ Buffer table
+ 3
+ 13
+
+
+
+
+
+
+
diff --git a/Src/XmlParser.cpp b/Src/XmlParser.cpp
index c44ded7..785bd25 100644
--- a/Src/XmlParser.cpp
+++ b/Src/XmlParser.cpp
@@ -2,5 +2,15 @@
#include
XmlParser::XmlParser(const std::string& inputFile){
- std::cout << inputFile;
+ xmlDocument.LoadFile(inputFile.c_str());
+}
+std::optional XmlParser::isError() const{
+ return xmlDocument.Error() ? std::optional(xmlDocument.ErrorStr()) : std::nullopt;
+}
+
+void XmlParser::parseXml(){
+ root = xmlDocument.FirstChildElement();
+ if(root == nullptr)
+ return;
+ std::cout << root->GetText();
}
\ No newline at end of file
diff --git a/Src/XmlParser.hpp b/Src/XmlParser.hpp
index ccd5545..ca7e6f9 100644
--- a/Src/XmlParser.hpp
+++ b/Src/XmlParser.hpp
@@ -3,12 +3,17 @@
#include
#include
+#include
+#include
struct XmlParser{
XmlParser(const std::string& inputFile);
+ std::optional isError() const;
+ void parseXml();
private:
-
+ tinyxml2::XMLDocument xmlDocument;
+ tinyxml2::XMLElement* root;
};
#endif
\ No newline at end of file
diff --git a/Src/main.cpp b/Src/main.cpp
index a2378be..9649e17 100644
--- a/Src/main.cpp
+++ b/Src/main.cpp
@@ -26,7 +26,13 @@ int main(int argc, char** argv){
}
catch(cxxopts::OptionException& ex){
std::cout << ex.what() << std::endl;
- return -1;
+ return 2;
}
+ //Try to parse the file
XmlParser xmlParser(inputFile);
+ if (auto err = xmlParser.isError()){
+ std::cout << "There was an error while reading " << inputFile << ":" << std::endl << *err << std::endl;
+ return 3;
+ }
+ xmlParser.parseXml();
}
\ No newline at end of file