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30 lines
493 B
Systemverilog
30 lines
493 B
Systemverilog
`default_nettype none
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module saw2sin
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( input var [15:0] i_saw
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, output var [15:0] o_sin
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);
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logic invert;
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always_comb invert = i_saw[15];
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logic reverse;
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always_comb reverse = i_saw[14];
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logic [15:0] qsaw;
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always_comb qsaw = reverse
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? {~i_saw[13:0], 2'b01} // Reverse
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: {i_saw[13:0], 2'b00}; // Normal
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logic [15:0] qsin;
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cordic cordic
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( .i_qph (qsaw)
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, .o_sin (qsin)
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);
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always_comb o_sin = invert
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? ~{1'b1, qsin[15:1]} + 1 // Invert
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: {1'b1, qsin[15:1]}; // Normal
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endmodule
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