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59 lines
1.7 KiB
Systemverilog
59 lines
1.7 KiB
Systemverilog
// V_erilator clock generation module, allows for the clock to be "stepped down" for use within the testbench
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// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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module generateClock
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( output var logic o_clk // Generated clock for testbench
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, input var logic i_rootClk // V_erilator clock input
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, input var logic [63:0] i_periodHi // Number of rootClk cycles-1 to stay high
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, input var logic [63:0] i_periodLo // Number of rootClk cycles-1 to stay low
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, input var logic [ 7:0] i_jitterControl // Random jitter control (0: none --> higher number: more jitter)
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);
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logic intClk_d;
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logic intClk_q;
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logic [63:0] downCounter_d;
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logic [63:0] downCounter_q;
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/* svlint off legacy_always */
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always @(posedge i_rootClk)
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intClk_q <= intClk_d;
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always @(posedge i_rootClk)
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downCounter_q <= downCounter_d;
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/* svlint on legacy_always */
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logic [7:0] rndJitter;
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always_ff @(posedge i_rootClk)
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/* verilator lint_off WIDTH */
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rndJitter <= $random;
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/* verilator lint_on WIDTH */
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logic jitterThisCycle;
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assign jitterThisCycle = (rndJitter < i_jitterControl);
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always_comb
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if (downCounter_q == '0)
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if (jitterThisCycle)
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downCounter_d = downCounter_q;
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else if (intClk_q)
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downCounter_d = i_periodLo;
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else
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downCounter_d = i_periodHi;
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else
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downCounter_d = downCounter_q - 'd1;
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always_comb
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if ((downCounter_q == '0) && !jitterThisCycle)
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intClk_d = ~intClk_q;
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else
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intClk_d = intClk_q;
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assign o_clk = intClk_q;
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endmodule
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`resetall
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