mirror of
https://github.com/supleed2/axiTest.git
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92 lines
2.5 KiB
Systemverilog
92 lines
2.5 KiB
Systemverilog
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// SystemVerilog testbench to instantiate AXI4-Lite driver and memory modules
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// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// Verilator Class support is limited but in active development. Verilator
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// supports members, and methods. Verilator does not support class static
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// members, class extend, or class parameters.
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module axiTest
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( input var logic i_clk
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, input var logic i_rst
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, input var logic i_arst
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);
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Axi4LiteSlave
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#(.AWIDTH (12 )
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, .DWIDTH (32 )
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) u_axiSlave
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( .i_aClk (aClk )
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, .i_aResetn (aResetn)
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// Read Address Channel (Master -> Slave)
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, .i_arValid (arValid)
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, .o_arReady (arReady)
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, .i_arAddr (arAddr )
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, .i_arProt (arProt )
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// Read Data Channel (Slave -> Master)
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, .o_rValid (rValid )
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, .i_rReady (rReady )
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, .o_rData (rData )
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, .o_rResp (rResp )
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// Write Address Channel (Master -> Slave)
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, .i_awValid (awValid)
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, .o_awReady (awReady)
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, .i_awAddr (awAddr )
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, .i_awProt (awProt )
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// Write Data Channel (Master -> Slave)
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, .i_wValid (wValid )
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, .o_wReady (wReady )
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, .i_wData (wData )
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, .i_wStrb (wStrb )
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// Write Response Channel (Slave -> Master)
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, .o_bValid (bValid )
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, .i_bReady (bReady )
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, .o_bResp (bResp )
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);
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generateClock u_generateClock
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( .o_clk (aClk ) // Generated clock for testbench
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, .i_rootClk (i_clk) // V_erilator clock input
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, .i_periodHi (0 ) // Number of rootClk cycles-1 to stay high
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, .i_periodLo (0 ) // Number of rootClk cycles-1 to stay low
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, .i_jitterControl (0 ) // Random jitter control (0: none --> higher number: more jitter)
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);
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Axi4LiteDriver
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#(.AWIDTH (12 )
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, .DWIDTH (32 )
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) u_axiDriver
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( .i_aClk (aClk )
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, .i_aResetn (aResetn)
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// Read Address Channel (Master -> Slave)
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, .o_arValid (arValid)
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, .i_arReady (arReady)
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, .o_arAddr (arAddr )
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, .o_arProt (arProt )
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// Read Data Channel (Slave -> Master)
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, .i_rValid (rValid )
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, .o_rReady (rReady )
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, .i_rData (rData )
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, .i_rResp (rResp )
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// Write Address Channel (Master -> Slave)
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, .o_awValid (awValid)
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, .i_awReady (awReady)
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, .o_awAddr (awAddr )
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, .o_awProt (awProt )
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// Write Data Channel (Master -> Slave)
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, .o_wValid (wValid )
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, .i_wReady (wReady )
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, .o_wData (wData )
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, .o_wStrb (wStrb )
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// Write Response Channel (Slave -> Master)
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, .i_bValid (bValid )
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, .o_bReady (bReady )
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, .i_bResp (bResp )
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);
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endmodule
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`resetall
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