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// Synthesizable DPI-C driver for APB Bus Interface
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
// Example Usage:
// ### test_DUT.sv (Instance) ###
// ApbDriver
// #(.APB_AW (32)
// , .APB_DW (32)
// , .APB_SW ( 4)
// ) u_apbDriver
// ( .ckApb (apbBus.ckApb )
// , .apbPRData (apbBus.apbPRData )
// , .apbPReady (apbBus.apbPReady )
// , .apbPSlvErr (apbBus.apbPSlvErr)
// , .apbPSel (apbBus.apbPSel )
// , .apbPEnable (apbBus.apbPEnable)
// , .apbPAddr (apbBus.apbPAddr )
// , .apbPWrite (apbBus.apbPWrite )
// , .apbPWData (apbBus.apbPWData )
// , .apbPStrb (apbBus.apbPStrb )
// , .apbPProt (apbBus.apbPProt )
// );
// ### test_DUT.cpp (Setup) ###
// #include <Vtest_DUT__Dpi.h>
// EITHER: VerilatorTbFst<Vtest_DUT>* tb = new VerilatorTbFst<Vtest_DUT>();
// OR : VerilatorTbVcd<Vtest_DUT>* tb = new VerilatorTbVcd<Vtest_DUT>();
// tb->setScope("test_DUT.u_apbDriver");
// ### test_DUT.cpp (Usage) ###
// uint32_t addr = 0x0100, data = 0x1234, strb = 0b1111, prot = 0b110;
// int err = 0;
// uint8_t SlvErr = 0;
// uint32_t readData = 0;
// err = tryStartApbWrite(&addr, &data, &strb, &prot);
// if (err != 0) { printf("tryStartApbWrite failed!\n"); }
// else {
// tb->ticks(2);
// err = tryFinishApbWrite(&SlvErr);
// while (err != 0) {
// printf("tryFinishApbWrite failed!\n");
// tb->tick();
// err = tryFinishApbWrite(&SlvErr);
// }
// if (SlvErr != 0) { printf("Apb Write failed!\n"); }
// }
// tb->tick();
// err = tryStartApbRead(&addr, &prot);
// if (err != 0) { printf("tryStartApbRead failed!\n"); }
// else {
// tb->ticks(2);
// err = tryFinishApbRead(&SlvErr, &readData);
// while (err != 0) {
// printf("tryFinishApbRead failed!\n");
// tb->tick();
// err = tryFinishApbRead(&SlvErr, &readData);
// }
// if (SlvErr != 0) { printf("Apb Read failed!\n"); }
// else { printf("Apb Read succeeded!\nExpected Read Data: 0x%x\nReceived Read Data: 0x%x\n", data, readData); }
// }
// tb->tick();
module ApbDriver
#(parameter int unsigned APB_AW = 32 // APB Address Width
, parameter int unsigned APB_DW = 32 // APB Data Width
, parameter int unsigned APB_SW = APB_DW/8 // APB Write Strobe Width
)(input var logic ckApb // -- Inputs to Driver
, input var logic [APB_DW-1:0] apbPRData
, input var logic apbPReady
, input var logic apbPSlvErr
, output var logic apbPSel // -- Outputs from Driver
, output var logic apbPEnable
, output var logic [APB_AW-1:0] apbPAddr
, output var logic apbPWrite
, output var logic [APB_DW-1:0] apbPWData
, output var logic [APB_SW-1:0] apbPStrb
, output var logic [2:0] apbPProt
);
// Delay-based version, does not allow for other accesses in C++ testbench
// while task is running, synthesizable version below is preferred
/*
export "DPI-C" task apbRead;
export "DPI-C" task apbWrite;
logic trComplete;
assign trComplete = ckApb & apbPReady;
task automatic apbRead (input bit [APB_AW-1:0] addr, input bit [2:0] prot, output bit SlvErr, output bit [APB_DW-1:0] RData);
@(posedge ckApb);
apbPSel = '1;
apbPEnable = '0;
apbPAddr = addr;
apbPWrite = '0;
apbPStrb = '0;
apbPProt = prot;
@(posedge ckApb);
apbPEnable = '1;
@(posedge trComplete);
apbPSel = '0;
RData = apbPRData;
SlvErr = apbPSlvErr;
endtask
task automatic apbWrite (input bit [APB_AW-1:0] addr, input bit [APB_DW-1:0] data, input bit [APB_SW-1:0] strb, input bit [2:0] prot, output bit SlvErr);
@(posedge ckApb);
apbPSel = '1;
apbPEnable = '0;
apbPAddr = addr;
apbPWrite = '1;
apbPWData = data;
apbPStrb = strb;
apbPProt = prot;
@(posedge ckApb);
apbPEnable = '1;
@(posedge trComplete);
apbPSel = '0;
SlvErr = apbPSlvErr;
endtask
*/
// Returns 0 if complete and -1 if bus was busy / not ready yet
export "DPI-C" function tryStartApbRead;
export "DPI-C" function tryStartApbWrite;
export "DPI-C" function tryFinishApbRead;
export "DPI-C" function tryFinishApbWrite;
enum bit [2:0]
{ IDLE
, R_SETUP
, R_ACCESS
, W_SETUP
, W_ACCESS
} apbState;
enum bit [1:0]
{ n_NONE
, n_IDLE
, n_READ
, n_WRITE
} nextState;
logic [APB_AW-1:0] nextAddr;
logic [APB_DW-1:0] nextWData;
logic [APB_SW-1:0] nextStrb;
logic [2:0] nextProt;
always_ff @(posedge ckApb) // apbPSel
case (apbState)
IDLE: apbPSel <= '0;
R_SETUP: apbPSel <= '1;
R_ACCESS: apbPSel <= '1;
W_SETUP: apbPSel <= '1;
W_ACCESS: apbPSel <= '1;
default: apbPSel <= '0;
endcase
always_ff @(posedge ckApb) // apbPEnable
case (apbState)
IDLE: apbPEnable <= '0;
R_SETUP: apbPEnable <= '0;
R_ACCESS: apbPEnable <= '1;
W_SETUP: apbPEnable <= '0;
W_ACCESS: apbPEnable <= '1;
default: apbPEnable <= '0;
endcase
always_ff @(posedge ckApb) // apbPAddr
case (apbState)
IDLE: apbPAddr <= '0;
R_SETUP: apbPAddr <= nextAddr;
R_ACCESS: apbPAddr <= nextAddr;
W_SETUP: apbPAddr <= nextAddr;
W_ACCESS: apbPAddr <= nextAddr;
default: apbPAddr <= '0;
endcase
always_ff @(posedge ckApb) // apbPWrite
case (apbState)
IDLE: apbPWrite <= '0;
R_SETUP: apbPWrite <= '0;
R_ACCESS: apbPWrite <= '0;
W_SETUP: apbPWrite <= '1;
W_ACCESS: apbPWrite <= '1;
default: apbPWrite <= '0;
endcase
always_ff @(posedge ckApb) // apbPWData
case (apbState)
IDLE: apbPWData <= '0;
R_SETUP: apbPWData <= '0;
R_ACCESS: apbPWData <= '0;
W_SETUP: apbPWData <= nextWData;
W_ACCESS: apbPWData <= nextWData;
default: apbPWData <= '0;
endcase
always_ff @(posedge ckApb) // apbPStrb
case (apbState)
IDLE: apbPStrb <= '0;
R_SETUP: apbPStrb <= '0;
R_ACCESS: apbPStrb <= '0;
W_SETUP: apbPStrb <= nextStrb;
W_ACCESS: apbPStrb <= nextStrb;
default: apbPStrb <= '0;
endcase
always_ff @(posedge ckApb) // apbPProt
case (apbState)
IDLE: apbPProt <= '0;
R_SETUP: apbPProt <= nextProt;
R_ACCESS: apbPProt <= nextProt;
W_SETUP: apbPProt <= nextProt;
W_ACCESS: apbPProt <= nextProt;
default: apbPProt <= '0;
endcase
always_ff @(posedge ckApb) // apbState
case (apbState)
IDLE: if (nextState == n_READ) apbState <= R_SETUP;
else if (nextState == n_WRITE) apbState <= W_SETUP;
else apbState <= IDLE;
R_SETUP: apbState <= R_ACCESS;
R_ACCESS: if (nextState == n_IDLE) apbState <= IDLE;
else apbState <= R_ACCESS;
W_SETUP: apbState <= W_ACCESS;
W_ACCESS: if (nextState == n_IDLE) apbState <= IDLE;
else apbState <= W_ACCESS;
default: apbState <= IDLE;
endcase
function automatic int tryStartApbRead (input bit [APB_AW-1:0] addr, input bit [2:0] prot);
if (apbState == IDLE && (nextState == n_NONE || nextState == n_IDLE)) begin
nextAddr = addr;
nextWData = '0;
nextStrb = '0;
nextProt = prot;
nextState = n_READ;
return 0;
end else
return -1;
endfunction
function automatic int tryStartApbWrite (input bit [APB_AW-1:0] addr, input bit [APB_DW-1:0] data, input bit [APB_SW-1:0] strb, input bit [2:0] prot);
if (apbState == IDLE && (nextState == n_NONE || nextState == n_IDLE)) begin
nextAddr = addr;
nextWData = data;
nextStrb = strb;
nextProt = prot;
nextState = n_WRITE;
return 0;
end else
return -1;
endfunction
function automatic int tryFinishApbRead (output bit SlvErr, output bit [APB_DW-1:0] RData);
if (apbState == R_ACCESS && apbPReady) begin
nextAddr = '0;
nextWData = '0;
nextStrb = '0;
nextProt = '0;
SlvErr = apbPSlvErr;
RData = apbPRData;
nextState = n_IDLE;
return 0;
end else
return -1;
endfunction
function automatic int tryFinishApbWrite (output bit SlvErr);
if (apbState == W_ACCESS && apbPReady) begin
nextAddr = '0;
nextWData = '0;
nextStrb = '0;
nextProt = '0;
SlvErr = apbPSlvErr;
nextState = n_IDLE;
return 0;
end else
return -1;
endfunction
endmodule
`resetall

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# apbDriver
Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.
The module allows for transactions to be started and stopped from within the C++ testbench, and functions execute in 0 time. Transactions cannot be queued but the function return code indicates success, so time can be advanced and the transaction attempted again in the case of failure.

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// Header file to be used in verilator C++ testbenches.
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
//
// Intended usage / order:
// - VerilatorTbFst<Vtest_DUT> *tb = new VerilatorTbFst<Vtest_DUT>();
// - tb->setClockPeriodPS(clock_period_in_picoseconds);
// - This value can be taken from within the SystemVerilog Testbench
// - tb->opentrace("output/test_DUT.verilator.fst");
// - tb->m_trace->dump(0);
// - Followed by arst/rst and signals matching the intended testbench flow.
#ifndef _VERILATORTBFST_H
#define _VERILATORTBFST_H
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <svdpi.h>
#include <verilated_fst_c.h>
typedef enum {
ERROR,
WARN,
NOTE
} TbPrintLevel;
template <class VA>
class VerilatorTbFst {
public:
VA *m_dut;
VerilatedFstC *m_trace;
uint64_t m_tickcount;
uint64_t m_clockperiod;
bool m_dodump;
VerilatorTbFst(void) : m_trace(NULL), m_tickcount(0l) {
m_dut = new VA;
Verilated::traceEverOn(true);
m_dut->i_clk = 0;
m_dut->i_rst = 1;
m_dodump = true;
eval(); // Get our initial values set properly.
}
virtual ~VerilatorTbFst(void) {
closetrace();
delete m_dut;
m_dut = NULL;
}
virtual void setClockPeriodPS(const uint64_t ps) {
m_clockperiod = ps;
}
virtual void opentrace(const char *fstname) {
opentrace(fstname, 99);
}
virtual void opentrace(const char *fstname, int tracedepth) {
if (!m_trace) {
m_trace = new VerilatedFstC;
m_dut->trace(m_trace, tracedepth);
m_trace->open(fstname);
}
}
virtual void closetrace(void) {
if (m_trace) {
m_trace->close();
delete m_trace;
m_trace = NULL;
}
}
virtual void eval(void) {
m_dut->eval();
}
// Call from loop {check, drive, tick}
virtual void tick(void) {
// check
// drive
// rise eval dump
// fall eval dump
m_dut->i_clk = 1;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount));
}
m_dut->i_clk = 0;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount + (m_clockperiod / 2)));
m_trace->flush();
}
m_tickcount++;
}
virtual void ticks(int numTicks) {
for (int i = 0; i < numTicks; i++)
tick();
}
virtual void areset(void) {
m_dut->i_arst = 0;
tick();
m_dut->i_arst = 1;
ticks(4);
m_dut->i_arst = 0;
}
virtual void reset(void) {
m_dut->i_rst = 1;
ticks(5);
m_dut->i_rst = 0;
}
unsigned long tickcount(void) {
return m_tickcount;
}
virtual bool done(void) {
return Verilated::gotFinish();
}
virtual void setScope(const char *scopeName) {
char fullScopeName[1024];
svSetScope(svGetScopeFromName(strcat(strcpy(fullScopeName, "TOP."), scopeName)));
}
};
#endif // _VERILATORTBFST_H

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// Example APB Slave for testing APB Driver module
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
module apbSlave
#(parameter int AWIDTH = 12
, parameter int DWIDTH = 32
, parameter int SWIDTH = DWIDTH/8
)(input var logic i_ck
, input var logic i_rst_n
, input var logic i_sel
, input var logic i_enable
, input var logic [AWIDTH-1:0] i_addr
, input var logic i_write
, input var logic [DWIDTH-1:0] i_wdata
, input var logic [SWIDTH-1:0] i_strb
, input var logic [2:0] i_prot
, output var logic [DWIDTH-1:0] o_rdata
, output var logic o_ready
, output var logic o_slverr
);
logic [DWIDTH-1:0] mem [4096];
logic [DWIDTH-1:0] wdata;
for (genvar i = 0; i < SWIDTH; i++) begin
assign wdata[8*i+7:8*i] = i_strb[i] ? i_wdata[8*i+7:8*i] : mem[i_addr][8*i+7:8*i];
end
enum bit [1:0]
{ SETUP
, WRITE
, READ
} STATE;
always_comb
case (STATE)
SETUP: begin
o_rdata = '0;
o_ready = '0;
o_slverr = '0;
end
WRITE: begin
o_rdata = '0;
o_ready = '1;
o_slverr = '0;
end
READ: begin
o_rdata = mem[i_addr];
o_ready = '1;
o_slverr = '0;
end
default: begin end
endcase
always_ff @(posedge i_ck)
if (i_rst_n == 0)
STATE <= SETUP;
else if (i_sel == 0)
STATE <= SETUP;
else
if (i_write == 0)
STATE <= READ;
else
STATE <= WRITE;
always_ff @(negedge i_ck)
if (STATE == WRITE) mem[i_addr] <= wdata;
else mem[i_addr] <= mem[i_addr];
endmodule
/* verilator lint_on UNUSED */
`resetall

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// Verilator testbench for testing the APB Driver
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
#include "VerilatorTbFst.h"
#include <VapbTest.h>
#include <VapbTest__Dpi.h>
#include <iostream>
#include <stdlib.h>
#include <string>
#include <svdpi.h>
#include <verilated.h>
#ifndef N_CYCLES
#define N_CYCLES 100
#endif
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
VerilatorTbFst<VapbTest> *tb = new VerilatorTbFst<VapbTest>();
tb->setScope("apbTest.u_apbDriver");
// Get SystemVerilog Parameters
const uint64_t CLOCK_PERIOD_PS = 10;
tb->setClockPeriodPS(2 * (CLOCK_PERIOD_PS / 3));
tb->opentrace("output/VapbTest.fst");
tb->m_trace->dump(0); // Initialize waveform at beginning of time.
printf("Starting!\n");
tb->m_dut->i_rst = 1;
tb->ticks(2);
tb->m_dut->i_rst = 0;
tb->ticks(2);
uint32_t addr, data, strb, prot;
int err = 0;
uint8_t SlvErr = 0;
uint32_t readData = 0;
addr = 0x100u;
data = 0x1234BEEFu;
strb = 0b1111u;
prot = 0b110u;
err = tryStartApbWrite(&addr, &data, &strb, &prot);
if (err != 0) {
printf("tryStartApbWrite failed!\n");
} else {
printf("tryStartApbWrite succeeded!\n");
tb->ticks(2);
err = tryFinishApbWrite(&SlvErr);
while (err != 0) {
printf("tryFinishApbWrite failed!\n");
tb->tick();
err = tryFinishApbWrite(&SlvErr);
}
printf("tryFinishApbWrite succeeded!\n");
if (SlvErr != 0) {
printf("Apb Write failed!\n");
} else {
printf("Apb Write succeeded!\n");
}
}
tb->tick();
tb->tick();
err = tryStartApbRead(&addr, &prot);
if (err != 0) {
printf("tryStartApbRead failed!\n");
} else {
printf("tryStartApbRead succeeded!\n");
tb->ticks(2);
err = tryFinishApbRead(&SlvErr, &readData);
while (err != 0) {
printf("tryFinishApbRead failed!\n");
tb->tick();
err = tryFinishApbRead(&SlvErr, &readData);
}
printf("tryFinishApbRead succeeded!\n");
if (SlvErr != 0) {
printf("Apb Read failed!\n");
} else {
printf("Apb Read succeeded!\nReceived Read Data: 0x%x\n", readData);
}
}
tb->tick();
tb->tick();
data = 0xDEAD5678u;
strb = 0b1100u;
err = tryStartApbWrite(&addr, &data, &strb, &prot);
if (err != 0) {
printf("tryStartApbWrite failed!\n");
} else {
printf("tryStartApbWrite succeeded!\n");
tb->ticks(2);
err = tryFinishApbWrite(&SlvErr);
while (err != 0) {
printf("tryFinishApbWrite failed!\n");
tb->tick();
err = tryFinishApbWrite(&SlvErr);
}
printf("tryFinishApbWrite succeeded!\n");
if (SlvErr != 0) {
printf("Apb Write failed!\n");
} else {
printf("Apb Write succeeded!\n");
}
}
tb->tick();
tb->tick();
err = tryStartApbRead(&addr, &prot);
if (err != 0) {
printf("tryStartApbRead failed!\n");
} else {
printf("tryStartApbRead succeeded!\n");
tb->ticks(2);
err = tryFinishApbRead(&SlvErr, &readData);
while (err != 0) {
printf("tryFinishApbRead failed!\n");
tb->tick();
err = tryFinishApbRead(&SlvErr, &readData);
}
printf("tryFinishApbRead succeeded!\n");
if (SlvErr != 0) {
printf("Apb Read failed!\n");
} else {
printf("Apb Read succeeded!\nExpected Read Data: 0x%x\nReceived Read Data: 0x%x\n", 0xDEADBEEFu, readData);
}
}
tb->tick();
tb->tick();
while (tb->tickcount() < N_CYCLES * 2) {
tb->ticks(2); // Run Tests
}
printf("Time: %ldns\n", tb->tickcount());
printf("Stopped.\n");
tb->closetrace();
exit(EXIT_SUCCESS);
}

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// SystemVerilog testbench to instantiate Driver and Slave modules
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
module apbTest
( input var logic i_clk
, input var logic i_rst
, input var logic i_arst
);
localparam int unsigned AddrWidth = 12;
localparam int unsigned DataWidth = 32;
localparam int unsigned StrbWidth = 4;
logic i_rst_n;
assign i_rst_n = !i_rst;
logic o_ck;
assign apbBus.ckApb = o_ck;
apbSlave
#(.AWIDTH (AddrWidth )
, .DWIDTH (DataWidth )
, .SWIDTH (StrbWidth )
) u_apbSlave
( .i_ck (apbBus.ckApb )
, .i_rst_n (i_rst_n )
, .i_sel (apbBus.apbPSel )
, .i_enable (apbBus.apbPEnable)
, .i_addr (apbBus.apbPAddr )
, .i_write (apbBus.apbPWrite )
, .i_wdata (apbBus.apbPWData )
, .i_strb (apbBus.apbPStrb )
, .i_prot (apbBus.apbPProt )
, .o_rdata (apbBus.apbPRData )
, .o_ready (apbBus.apbPReady )
, .o_slverr (apbBus.apbPSlvErr)
);
generateClock u_generateClock
( .o_clk (o_ck ) // Generated clock for testbench
, .i_rootClk (i_clk) // V_erilator clock input
, .i_periodHi (0 ) // Number of rootClk cycles-1 to stay high
, .i_periodLo (0 ) // Number of rootClk cycles-1 to stay low
, .i_jitterControl (0 ) // Random jitter control (0: none --> higher number: more jitter)
);
in_ApbBus
#(.APB_DW (DataWidth)
, .APB_AW (AddrWidth)
) apbBus ();
ApbDriver
#(.APB_AW (AddrWidth )
, .APB_DW (DataWidth )
, .APB_SW (StrbWidth )
) u_apbDriver
( .ckApb (apbBus.ckApb )
, .apbPRData (apbBus.apbPRData )
, .apbPReady (apbBus.apbPReady )
, .apbPSlvErr (apbBus.apbPSlvErr)
, .apbPSel (apbBus.apbPSel )
, .apbPEnable (apbBus.apbPEnable)
, .apbPAddr (apbBus.apbPAddr )
, .apbPWrite (apbBus.apbPWrite )
, .apbPWData (apbBus.apbPWData )
, .apbPStrb (apbBus.apbPStrb )
, .apbPProt (apbBus.apbPProt )
);
endmodule
/* verilator lint_on UNUSED */
`resetall

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// V_erilator clock generation module, allows for the clock to be "stepped down" for use within the testbench
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
module generateClock
( output var logic o_clk // Generated clock for testbench
, input var logic i_rootClk // V_erilator clock input
, input var logic [63:0] i_periodHi // Number of rootClk cycles-1 to stay high
, input var logic [63:0] i_periodLo // Number of rootClk cycles-1 to stay low
, input var logic [ 7:0] i_jitterControl // Random jitter control (0: none --> higher number: more jitter)
);
logic intClk_d;
logic intClk_q;
logic [63:0] downCounter_d;
logic [63:0] downCounter_q;
/* svlint off legacy_always */
always @(posedge i_rootClk)
intClk_q <= intClk_d;
always @(posedge i_rootClk)
downCounter_q <= downCounter_d;
/* svlint on legacy_always */
logic [7:0] rndJitter;
always_ff @(posedge i_rootClk)
/* verilator lint_off WIDTH */
rndJitter <= $random;
/* verilator lint_on WIDTH */
logic jitterThisCycle;
assign jitterThisCycle = (rndJitter < i_jitterControl);
always_comb
if (downCounter_q == '0)
if (jitterThisCycle)
downCounter_d = downCounter_q;
else if (intClk_q)
downCounter_d = i_periodLo;
else
downCounter_d = i_periodHi;
else
downCounter_d = downCounter_q - 'd1;
always_comb
if ((downCounter_q == '0) && !jitterThisCycle)
intClk_d = ~intClk_q;
else
intClk_d = intClk_q;
assign o_clk = intClk_q;
endmodule
`resetall

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// Interface for APB, no modports were used
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
interface in_ApbBus;
event transactionReady; //
event transactionComplete; //
parameter int unsigned APB_AW = 32; // APB Address Width
parameter int unsigned APB_DW = 32; // APB Data Width
parameter int unsigned APB_SW = APB_DW/8; // APB Write Strobe Width
parameter int unsigned APB_AUSER = 0; // Address User Width, set to 0 when unused
localparam int unsigned APB_AU_BITS = (APB_AUSER == 0) ? 1 : APB_AUSER; // Number of bits in address user (auto-computed, do not override)
logic arstApb_n; //
logic ckApb; //
logic [APB_AW-1:0] apbPAddr; //
logic [2:0] apbPProt; //
logic apbPSel; //
logic apbPEnable; //
logic apbPWrite; //
logic [APB_DW-1:0] apbPWData; //
logic [APB_SW-1:0] apbPStrb; //
logic [APB_AU_BITS-1:0] apbPAUser; //
logic [APB_DW-1:0] apbPRData; //
logic apbPSlvErr; //
logic apbPReady; //
endinterface
/* verilator lint_on UNUSED */
`resetall

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#!/usr/bin/env bash
rm output/*
mkdir -p output
verilator --trace-fst -DUSE_FST -CFLAGS -DUSEFST --cc --exe --default-language 1800-2017 --trace-depth 5 -DN_CYCLES=25 -CFLAGS -DN_CYCLES=25 --Mdir output -Wall apbTest.cpp apbTest.sv
make -C output -f VapbTest.mk VapbTest
time output/VapbTest > output/verilator.log
! grep -q ERROR output/verilator.log