mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
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247 lines
7.7 KiB
Systemverilog
247 lines
7.7 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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//END USER LICENCE AGREEMENT //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
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//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
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//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
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//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
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// //
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//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
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//a non-exclusive, worldwide, non-transferable, copyright licence only to //
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//redistribute and use in source and binary forms, with or without modification,//
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//for academic purposes provided the following conditions are met: //
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//a) Redistributions of source code must retain the above copyright notice, this//
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//list of conditions and the following disclaimer. //
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//b) Redistributions in binary form must reproduce the above copyright notice, //
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//this list of conditions and the following disclaimer in the documentation //
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//and/or other materials provided with the distribution. //
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// //
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//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
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//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
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//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
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//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
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//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
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//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
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//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
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//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
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//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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module AHBVGA_SVA(
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input wire HCLK,
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input wire HRESETn,
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input wire [31:0] HADDR,
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input wire [31:0] HWDATA,
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input wire HREADY,
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input wire HWRITE,
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input wire [1:0] HTRANS,
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input wire HSEL,
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output wire [31:0] HRDATA,
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output wire HREADYOUT,
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output wire HSYNC,
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output wire VSYNC,
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output wire [7:0] RGB
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);
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//Register locations
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localparam IMAGEADDR = 4'hA;
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localparam CONSOLEADDR = 4'h0;
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//Internal AHB signals
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reg last_HWRITE;
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reg last_HSEL;
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reg [1:0] last_HTRANS;
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reg [31:0] last_HADDR;
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wire [7:0] console_rgb; //console rgb signal
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wire [9:0] pixel_x; //current x pixel
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wire [9:0] pixel_y; //current y pixel
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reg console_write; //write to console
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reg [7:0] console_wdata;//data to write to console
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reg image_write; //write to image
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reg [7:0] image_wdata; //data to write to image
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wire [7:0] image_rgb; //image color
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wire scroll; //scrolling signal
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wire sel_console;
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wire sel_image;
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reg [7:0] cin;
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always @(posedge HCLK)
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if(HREADY)
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begin
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last_HADDR <= HADDR;
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last_HWRITE <= HWRITE;
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last_HSEL <= HSEL;
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last_HTRANS <= HTRANS;
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end
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//Give time for the screen to refresh before writing
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assign HREADYOUT = ~scroll;
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//VGA interface: control the synchronization and color signals for a particular resolution
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VGAInterface uVGAInterface (
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.CLK(HCLK),
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.resetn(HRESETn),
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.COLOUR_IN(cin),
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.cout(RGB),
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.hs(HSYNC),
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.vs(VSYNC),
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.addrh(pixel_x),
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.addrv(pixel_y)
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);
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//VGA console module: output the pixels in the text region
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vga_console uvga_console(
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.clk(HCLK),
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.resetn(HRESETn),
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.pixel_x(pixel_x),
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.pixel_y(pixel_y),
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.text_rgb(console_rgb),
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.font_we(console_write),
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.font_data(console_wdata),
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.scroll(scroll)
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);
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//VGA image buffer: output the pixels in the image region
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vga_image uvga_image(
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.clk(HCLK),
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.resetn(HRESETn),
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.address(last_HADDR[15:2]),
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.pixel_x(pixel_x),
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.pixel_y(pixel_y),
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.image_we(image_write),
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.image_data(image_wdata),
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.image_rgb(image_rgb)
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);
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assign sel_console = (last_HADDR[23:0]== 12'h000000000000);
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assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
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//Set console write and write data
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always @(posedge HCLK, negedge HRESETn)
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begin
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if(!HRESETn)
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begin
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console_write <= 0;
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console_wdata <= 0;
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end
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else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console)
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begin
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console_write <= 1'b1;
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console_wdata <= HWDATA[7:0];
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end
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else
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begin
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console_write <= 1'b0;
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console_wdata <= 0;
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end
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end
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//Set image write and image write data
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always @(posedge HCLK, negedge HRESETn)
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begin
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if(!HRESETn)
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begin
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image_write <= 0;
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image_wdata <= 0;
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end
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else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image)
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begin
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image_write <= 1'b1;
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image_wdata <= HWDATA[7:0];
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end
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else
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begin
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image_write <= 1'b0;
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image_wdata <= 0;
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end
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end
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//Select the rgb color for a particular region
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always @*
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begin
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if(!HRESETn)
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cin <= 8'h00;
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else
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if(pixel_x[9:0]< 240 )
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cin <= console_rgb ;
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else
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cin <= image_rgb;
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end
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//Assertions and verification
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int hcounter;
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int vcounter;
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always_ff @(posedge HCLK)
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begin
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if(!HRESETn)
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begin
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hcounter <= 0;
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vcounter <= 0;
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end
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else
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begin
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if($fell(VSYNC))
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vcounter <= 0;
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else
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if($fell(HSYNC))
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vcounter <= vcounter + 1;
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if($fell(HSYNC))
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hcounter <= 0;
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else
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hcounter <= hcounter + 1;
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end
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end
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assert_display_range_x: assert property
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( @(posedge HCLK) disable iff(!HRESETn)
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0 <= pixel_x <= 640
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);
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assert_display_range_y: assert property
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( @(posedge HCLK) disable iff(!HRESETn)
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0 <= pixel_y <= 480
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);
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assert_vsync_pulse_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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$rose(VSYNC) -> (($past(vcounter,1) == 8'h1) || (vcounter == '0))
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);
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assert_hsync_pulse_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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($rose(HSYNC) && !$rose(VSYNC) && VSYNC) -> ($past(hcounter,1)/2 == 8'd95)
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);
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assert_line_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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($fell(HSYNC) && !$rose(VSYNC) && VSYNC) -> ($past(hcounter,1)/2 == 800)
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);
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assert_frame_timer: assert property
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(
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@(posedge HCLK) disable iff (!HRESETn)
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$fell(VSYNC) -> (($past(vcounter,1) == (32'd480 + 32'd10 + 32'd2 + 32'd29)) || (vcounter == '0))
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);
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endmodule
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