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ahblite_sys.vc Normal file
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rtl/AHBLITE_SYS.v
rtl/AHB_BRAM/AHB2BRAM.v
rtl/AHB_BUS/AHBDCD.v
rtl/AHB_BUS/AHBMUX.v
rtl/AHB_GPIO/AHBGPIO.v
rtl/AHB_VGA/AHBVGASYS.v
rtl/CortexM0-DS/cortexm0ds_logic.v
rtl/CortexM0-DS/CORTEXM0INTEGRATION.v
tbench/ahblite_sys_tb.v

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docs/AHB Peripherals Presentation.pdf Normal file
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docs/AHB Peripherals Specification.pdf Normal file
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docs/AHB_Lite_Spec.pdf Normal file
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docs/HW_Verification_Main_Coursework.pdf Normal file
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For simulation purposes, place the code.hex file in the same root directory where you launch the Questasim simulation

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBLITE_SYS(
//CLOCKS & RESET
input wire CLK,
input wire RESET,
//TO BOARD LEDs
output wire [7:0] LED,
// Switch Inputs
input wire [7:0] SW,
//VGA IO
output wire [2:0] VGARED,
output wire [2:0] VGAGREEN,
output wire [1:0] VGABLUE,
output wire HSYNC, //VGA Horizontal Sync
output wire VSYNC, //VGA Vertical Sync
// Debug
input wire TCK_SWCLK, // SWD Clk / JTAG TCK
input wire TDI_NC, // NC / JTAG TDI
inout wire TMS_SWDIO, // SWD I/O / JTAG TMS
output wire TDO_SWO // SW Out / JTAG TDO
);
//AHB-LITE SIGNALS
//Global Signals
wire HCLK;
wire HRESETn;
//Address, Control & Write Data Signals
wire [31:0] HADDR;
wire [31:0] HWDATA;
wire HWRITE;
wire [1:0] HTRANS;
wire [2:0] HBURST;
wire HMASTLOCK;
wire [3:0] HPROT;
wire [2:0] HSIZE;
//Transfer Response & Read Data Signals
wire [31:0] HRDATA;
wire HRESP;
wire HREADY;
//SELECT SIGNALS
wire [3:0] MUX_SEL;
wire HSEL_MEM;
wire HSEL_GPIO;
wire HSEL_VGA;
//SLAVE READ DATA
wire [31:0] HRDATA_MEM;
wire [31:0] HRDATA_GPIO;
wire [31:0] HRDATA_VGA;
//SLAVE HREADYOUT
wire HREADYOUT_MEM;
wire HREADYOUT_GPIO;
wire HREADYOUT_VGA;
//CM0-DS Sideband signals
wire [31:0] IRQ;
// CM-DS Sideband signals
wire lockup;
wire lockup_reset_req;
wire sys_reset_req;
//SYSTEM GENERATES NO ERROR RESPONSE
assign HRESP = 1'b0;
// Interrupt signals
assign IRQ = 32'h00000000;
// Clock
wire fclk; // Free running clock
// Reset
wire reset_n = RESET;
// Clock divider, divide the frequency by two, hence less time constraint
reg clk_div;
always @(posedge CLK)
begin
clk_div=~clk_div;
end
assign fclk = clk_div;
// Reset synchronizer
reg [4:0] reset_sync_reg;
assign lockup_reset_req = 1'b0;
always @(posedge fclk or negedge reset_n)
begin
if (!reset_n)
reset_sync_reg <= 5'b00000;
else
begin
reset_sync_reg[3:0] <= {reset_sync_reg[2:0], 1'b1};
reset_sync_reg[4] <= reset_sync_reg[2] &
(~(sys_reset_req | (lockup & lockup_reset_req)));
end
end
// CPU System Bus
assign HCLK = fclk;
assign HRESETn = reset_sync_reg[4];
// Debug signals (DesignStart Cortex-M0 supports only SWD)
wire dbg_swdo_en;
wire dbg_swdo;
wire dbg_swdi;
assign TMS_SWDIO = dbg_swdo_en ? dbg_swdo : 1'bz;
assign dbg_swdi = TMS_SWDIO;
wire cdbgpwrupreq2ack;
// DesignStart simplified integration level
CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION (
// CLOCK AND RESETS
.FCLK (fclk),
.SCLK (fclk),
.HCLK (fclk),
.DCLK (fclk),
.PORESETn (reset_sync_reg[2]),
.DBGRESETn (reset_sync_reg[3]),
.HRESETn (HRESETn),
.SWCLKTCK (TCK_SWCLK),
.nTRST (1'b1),
// AHB-LITE MASTER PORT
.HADDR (HADDR),
.HBURST (HBURST),
.HMASTLOCK (HMASTLOCK),
.HPROT (HPROT),
.HSIZE (HSIZE),
.HTRANS (HTRANS),
.HWDATA (HWDATA),
.HWRITE (HWRITE),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
.HMASTER (),
// CODE SEQUENTIALITY AND SPECULATION
.CODENSEQ (),
.CODEHINTDE (),
.SPECHTRANS (),
// DEBUG
.SWDITMS (dbg_swdi),
.TDI (TDI_NS),
.SWDO (dbg_swdo),
.SWDOEN (dbg_swdo_en),
.TDO (TDO_SWO),
.nTDOEN (),
.DBGRESTART (1'b0),
.DBGRESTARTED (),
.EDBGRQ (1'b0), // External Debug request to CPU
.HALTED (),
// MISC
.NMI (1'b0), // Non-maskable interrupt input
.IRQ (IRQ), // Interrupt request inputs
.TXEV (), // Event output (SEV executed)
.RXEV (1'b0), // Event input
.LOCKUP (lockup), // Core is locked-up
.SYSRESETREQ (sys_reset_req), // System reset request
.STCALIB ({1'b1, // No alternative clock source
1'b0, // Exact multiple of 10ms from FCLK
24'h007A11F}), // Calibration value for SysTick for 50 MHz source
.STCLKEN (1'b0), // SysTick SCLK clock disable
.IRQLATENCY (8'h00),
.ECOREVNUM (28'h0),
// POWER MANAGEMENT
.GATEHCLK (),
.SLEEPING (), // Core and NVIC sleeping
.SLEEPDEEP (),
.WAKEUP (),
.WICSENSE (),
.SLEEPHOLDREQn (1'b1),
.SLEEPHOLDACKn (),
.WICENREQ (1'b0),
.WICENACK (),
.CDBGPWRUPREQ (cdbgpwrupreq2ack),
.CDBGPWRUPACK (cdbgpwrupreq2ack),
// SCAN IO
.SE (1'b0),
.RSTBYPASS (1'b0)
);
//Address Decoder
AHBDCD uAHBDCD (
.HADDR(HADDR[31:0]),
.HSEL_S0(HSEL_MEM),
.HSEL_S1(HSEL_VGA),
.HSEL_S2(),
.HSEL_S3(),
.HSEL_S4(HSEL_GPIO),
.HSEL_S5(),
.HSEL_S6(),
.HSEL_S7(),
.HSEL_S8(),
.HSEL_S9(),
.HSEL_NOMAP(),
.MUX_SEL(MUX_SEL[3:0])
);
//Slave to Master Mulitplexor
AHBMUX uAHBMUX (
.HCLK(HCLK),
.HRESETn(HRESETn),
.MUX_SEL(MUX_SEL[3:0]),
.HRDATA_S0(HRDATA_MEM),
.HRDATA_S1(HRDATA_VGA),
.HRDATA_S2(32'h00000000),
.HRDATA_S3(32'h00000000),
.HRDATA_S4(HRDATA_GPIO),
.HRDATA_S5(32'h00000000),
.HRDATA_S6(32'h00000000),
.HRDATA_S7(32'h00000000),
.HRDATA_S8(32'h00000000),
.HRDATA_S9(32'h00000000),
.HRDATA_NOMAP(32'hDEADBEEF),
.HREADYOUT_S0(HREADYOUT_MEM),
.HREADYOUT_S1(HREADYOUT_VGA),
.HREADYOUT_S2(1'b1),
.HREADYOUT_S3(1'b1),
.HREADYOUT_S4(HREADYOUT_GPIO),
.HREADYOUT_S5(1'b1),
.HREADYOUT_S6(1'b1),
.HREADYOUT_S7(1'b1),
.HREADYOUT_S8(1'b1),
.HREADYOUT_S9(1'b1),
.HREADYOUT_NOMAP(1'b1),
.HRDATA(HRDATA[31:0]),
.HREADY(HREADY)
);
// AHBLite Peripherals
// AHB-Lite RAM
AHB2MEM uAHB2MEM (
//AHBLITE Signals
.HSEL(HSEL_MEM),
.HCLK(HCLK),
.HRESETn(HRESETn),
.HREADY(HREADY),
.HADDR(HADDR),
.HTRANS(HTRANS[1:0]),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HWDATA(HWDATA[31:0]),
.HRDATA(HRDATA_MEM),
.HREADYOUT(HREADYOUT_MEM)
);
// AHBLite VGA Peripheral
AHBVGA uAHBVGA (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HREADY(HREADY),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HSEL(HSEL_VGA),
.HRDATA(HRDATA_VGA),
.HREADYOUT(HREADYOUT_VGA),
.HSYNC(HSYNC),
.VSYNC(VSYNC),
.RGB({VGARED,VGAGREEN,VGABLUE})
);
// AHBLite GPIO
AHBGPIO uAHBGPIO(
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HREADY(HREADY),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HSEL(HSEL_GPIO),
.HRDATA(HRDATA_GPIO),
.HREADYOUT(HREADYOUT_GPIO),
.GPIOIN({8'b00000000,SW[7:0]}),
.GPIOOUT(LED[7:0])
);
endmodule

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rtl/AHB_BRAM/AHB2BRAM.v Normal file
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// --========================================================================--
// Version and Release Control Information:
//
// File Name : AHB2BRAM.v
// File Revision : 1.60
//
// ----------------------------------------------------------------------------
// Purpose : Basic AHBLITE Internal Memory Default Size = 16KB
//
// --========================================================================--
module AHB2MEM
#(parameter MEMWIDTH = 14) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries]
(
//AHBLITE INTERFACE
//Slave Select Signals
input wire HSEL,
//Global Signal
input wire HCLK,
input wire HRESETn,
//Address, Control & Write Data
input wire HREADY,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [31:0] HWDATA,
// Transfer Response & Read Data
output wire HREADYOUT,
output reg [31:0] HRDATA
);
assign HREADYOUT = 1'b1; // Always ready
// Memory Array
reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
initial
begin
$readmemh("code.hex", memory);
end
// Registers to store Adress Phase Signals
reg APhase_HSEL;
reg APhase_HWRITE;
reg [1:0] APhase_HTRANS;
reg [31:0] APhase_HRADDR;
reg [31:0] APhase_HWADDR;
reg [2:0] APhase_HSIZE;
// Sample the Address Phase
always @(posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
begin
APhase_HSEL <= 1'b0;
APhase_HWRITE <= 1'b0;
APhase_HTRANS <= 2'b00;
APhase_HWADDR <= 32'h0;
APhase_HSIZE <= 3'b000;
APhase_HRADDR[MEMWIDTH-2:0] <= {(MEMWIDTH-1){1'b0}};
end
else if(HREADY)
begin
APhase_HSEL <= HSEL;
APhase_HWRITE <= HWRITE;
APhase_HTRANS <= HTRANS;
APhase_HWADDR <= HADDR;
APhase_HSIZE <= HSIZE;
APhase_HRADDR[MEMWIDTH-2:0] <= HADDR[MEMWIDTH:2];
end
end
// Decode the bytes lanes depending on HSIZE & HADDR[1:0]
wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0];
wire tx_word = APhase_HSIZE[1];
wire byte_at_00 = tx_byte & ~APhase_HWADDR[1] & ~APhase_HWADDR[0];
wire byte_at_01 = tx_byte & ~APhase_HWADDR[1] & APhase_HWADDR[0];
wire byte_at_10 = tx_byte & APhase_HWADDR[1] & ~APhase_HWADDR[0];
wire byte_at_11 = tx_byte & APhase_HWADDR[1] & APhase_HWADDR[0];
wire half_at_00 = tx_half & ~APhase_HWADDR[1];
wire half_at_10 = tx_half & APhase_HWADDR[1];
wire word_at_00 = tx_word;
wire byte0 = word_at_00 | half_at_00 | byte_at_00;
wire byte1 = word_at_00 | half_at_00 | byte_at_01;
wire byte2 = word_at_00 | half_at_10 | byte_at_10;
wire byte3 = word_at_00 | half_at_10 | byte_at_11;
always @ (posedge HCLK)
begin
if(APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1])
begin
if(byte0)
memory[APhase_HWADDR[MEMWIDTH:2]][ 7: 0] <= HWDATA[ 7: 0];
if(byte1)
memory[APhase_HWADDR[MEMWIDTH:2]][15: 8] <= HWDATA[15: 8];
if(byte2)
memory[APhase_HWADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16];
if(byte3)
memory[APhase_HWADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24];
end
HRDATA = memory[HADDR[MEMWIDTH:2]];
end
endmodule

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rtl/AHB_BRAM/code.hex Normal file
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00003FFC
00000081
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
4A1E491D
60082054
491B6010
20454A1B
60106008
4A194918
60082053
49166010
20544A16
60106008
48164915
49166008
60082007
20004915
49156008
4913680A
60082001
600A4912
680B4912
00180C1B
40104A11
60084911
4A0F0918
49104010
0A186008
40104A0C
6008490E
4A0A0B18
490D4010
E7DD6008
50000000
51000000
52000000
FFFFFFFF
52000008
53000004
53000000
52000004
0000000F
54000000
54000004
54000008
5400000C

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Note that when synthesizing, "code.hex" and "AHB2BRAM.v" have to be placed at the same directory in your project.

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rtl/AHB_BUS/AHBDCD.v Normal file
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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBDCD(
input wire [31:0] HADDR,
output wire HSEL_S0,
output wire HSEL_S1,
output wire HSEL_S2,
output wire HSEL_S3,
output wire HSEL_S4,
output wire HSEL_S5,
output wire HSEL_S6,
output wire HSEL_S7,
output wire HSEL_S8,
output wire HSEL_S9,
output wire HSEL_NOMAP,
output reg [3:0] MUX_SEL
);
reg [15:0] dec;
//REFER CM0-DS REFERENC MANUAL FOR RAM & PERIPHERAL MEMORY MAP
// //MEMORY MAP --> START ADDR END ADDR SIZE
assign HSEL_S0 = dec[0]; //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MB
assign HSEL_S1 = dec[1]; //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MB
assign HSEL_S2 = dec[2]; //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MB
assign HSEL_S3 = dec[3]; //MEMORY MAP --> 0x5200_0000 to 0x52FF_FFFF 16MB
assign HSEL_S4 = dec[4]; //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MB
assign HSEL_S5 = dec[5]; //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MB
assign HSEL_S6 = dec[6]; //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MB
assign HSEL_S7 = dec[7]; //MEMORY MAP --> 0x5600_0000 to 0x56FF_FFFF 16MB
assign HSEL_S8 = dec[8]; //MEMORY MAP --> 0x5700_0000 to 0x57FF_FFFF 16MB
assign HSEL_S9 = dec[9]; //MEMORY MAP --> 0x5800_0000 to 0x58FF_FFFF 16MB
assign HSEL_NOMAP = dec[15]; //REST OF REGION NOT COVERED ABOVE
always@*
begin
case(HADDR[31:24])
8'h00: //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MB
begin
dec = 16'b0000_0000_00000001;
MUX_SEL = 4'b0000;
end
8'h50: //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MB
begin
dec = 16'b0000_0000_0000_0010;
MUX_SEL = 4'b0001;
end
8'h51: //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MB
begin
dec =16'b0000_0000_0000_0100;
MUX_SEL = 4'b0010;
end
8'h52: //MEMORY MAP --> 0x5200_0000 to 0x52FF_FFFF 16MB
begin
dec = 16'b0000_0000_0000_1000;
MUX_SEL = 4'b0011;
end
8'h53: //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MB
begin
dec = 16'b0000_0000_0001_0000;
MUX_SEL = 4'b0100;
end
8'h54: //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MB
begin
dec = 16'b0000_0000_0010_0000;
MUX_SEL = 4'b0101;
end
8'h55: //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MB
begin
dec = 16'b0000_0000_0100_0000;
MUX_SEL = 4'b0110;
end
8'h56: //MEMORY MAP --> 0x5600_0000 to 0x56FF_FFFF 16MB
begin
dec = 16'b0000_0000_1000_0000;
MUX_SEL = 4'b0111;
end
8'h57: //MEMORY MAP --> 0x5700_0000 to 0x57FF_FFFF 16MB
begin
dec = 16'b0000_0001_0000_0000;
MUX_SEL = 4'b1000;
end
8'h58: //MEMORY MAP --> 0x5800_0000 to 0x58FF_FFFF 16MB
begin
dec = 16'b0000_0010_0000_0000;
MUX_SEL = 4'b1001;
end
default: //NOMAP
begin
dec = 16'b1000_0000_00000000;
MUX_SEL = 4'b1111;
end
endcase
end
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBMUX(
//GLOBAL CLOCK & RESET
input wire HCLK,
input wire HRESETn,
//MUX SELECT FROM ADDRESS DECODER
input wire [3:0] MUX_SEL,
//READ DATA FROM ALL THE SLAVES
input wire [31:0] HRDATA_S0,
input wire [31:0] HRDATA_S1,
input wire [31:0] HRDATA_S2,
input wire [31:0] HRDATA_S3,
input wire [31:0] HRDATA_S4,
input wire [31:0] HRDATA_S5,
input wire [31:0] HRDATA_S6,
input wire [31:0] HRDATA_S7,
input wire [31:0] HRDATA_S8,
input wire [31:0] HRDATA_S9,
input wire [31:0] HRDATA_NOMAP,
//READYOUT FROM ALL THE SLAVES
input wire HREADYOUT_S0,
input wire HREADYOUT_S1,
input wire HREADYOUT_S2,
input wire HREADYOUT_S3,
input wire HREADYOUT_S4,
input wire HREADYOUT_S5,
input wire HREADYOUT_S6,
input wire HREADYOUT_S7,
input wire HREADYOUT_S8,
input wire HREADYOUT_S9,
input wire HREADYOUT_NOMAP,
//MULTIPLEXED HREADY & HRDATA TO MASTER
output reg HREADY,
output reg [31:0] HRDATA
);
reg [3:0] APHASE_MUX_SEL; // LATCH THE ADDRESS PHASE MUX_SELECT
// TO SEND THE APPROPRIATE RESPONSE & RDATA
// IN THE DATA PHASE
always@ (posedge HCLK or negedge HRESETn)
begin
if(!HRESETn)
APHASE_MUX_SEL <= 4'h0;
else if(HREADY) // NOTE: ALL THE CONTROL SIGNALS ARE VALID ONLY IF HREADY = 1'b1
APHASE_MUX_SEL <= MUX_SEL;
end
always@*
begin
case(APHASE_MUX_SEL)
4'b0000: begin // SELECT SLAVE0 RESPONSE & DATA IF PREVIOUS APHASE WAS FOR S0
HRDATA = HRDATA_S0;
HREADY = HREADYOUT_S0;
end
4'b0001: begin
HRDATA = HRDATA_S1;
HREADY = HREADYOUT_S1;
end
4'b0010: begin
HRDATA = HRDATA_S2;
HREADY = HREADYOUT_S2;
end
4'b0011: begin
HRDATA = HRDATA_S3;
HREADY = HREADYOUT_S3;
end
4'b0100: begin
HRDATA = HRDATA_S4;
HREADY = HREADYOUT_S4;
end
4'b0101: begin
HRDATA = HRDATA_S5;
HREADY = HREADYOUT_S5;
end
4'b0110: begin
HRDATA = HRDATA_S6;
HREADY = HREADYOUT_S6;
end
4'b0111: begin
HRDATA = HRDATA_S7;
HREADY = HREADYOUT_S7;
end
4'b1000: begin
HRDATA = HRDATA_S8;
HREADY = HREADYOUT_S8;
end
4'b1001: begin
HRDATA = HRDATA_S9;
HREADY = HREADYOUT_S9;
end
default: begin
HRDATA = HRDATA_NOMAP;
HREADY = HREADYOUT_NOMAP;
end
endcase
end
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBGPIO(
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [1:0] HTRANS,
input wire [31:0] HWDATA,
input wire HWRITE,
input wire HSEL,
input wire HREADY,
input wire [15:0] GPIOIN,
//Output
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire [15:0] GPIOOUT
);
localparam [7:0] gpio_data_addr = 8'h00;
localparam [7:0] gpio_dir_addr = 8'h04;
reg [15:0] gpio_dataout;
reg [15:0] gpio_datain;
reg [15:0] gpio_dir;
reg [15:0] gpio_data_next;
reg [31:0] last_HADDR;
reg [1:0] last_HTRANS;
reg last_HWRITE;
reg last_HSEL;
integer i;
assign HREADYOUT = 1'b1;
// Set Registers from address phase
always @(posedge HCLK)
begin
if(HREADY)
begin
last_HADDR <= HADDR;
last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
end
end
// Update in/out switch
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_dir <= 16'h0000;
end
else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dir <= HWDATA[15:0];
end
// Update output value
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_dataout <= 16'h0000;
end
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dataout <= HWDATA[15:0];
end
// Update input value
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
gpio_datain <= 16'h0000;
end
else if (gpio_dir == 16'h0000)
gpio_datain <= GPIOIN;
else if (gpio_dir == 16'h0001)
gpio_datain <= GPIOOUT;
end
assign HRDATA[15:0] = gpio_datain;
assign GPIOOUT = gpio_dataout;
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module AHBVGA(
input wire HCLK,
input wire HRESETn,
input wire [31:0] HADDR,
input wire [31:0] HWDATA,
input wire HREADY,
input wire HWRITE,
input wire [1:0] HTRANS,
input wire HSEL,
output wire [31:0] HRDATA,
output wire HREADYOUT,
output wire HSYNC,
output wire VSYNC,
output wire [7:0] RGB
);
//Register locations
localparam IMAGEADDR = 4'hA;
localparam CONSOLEADDR = 4'h0;
//Internal AHB signals
reg last_HWRITE;
reg last_HSEL;
reg [1:0] last_HTRANS;
reg [31:0] last_HADDR;
wire [7:0] console_rgb; //console rgb signal
wire [9:0] pixel_x; //current x pixel
wire [9:0] pixel_y; //current y pixel
reg console_write; //write to console
reg [7:0] console_wdata;//data to write to console
reg image_write; //write to image
reg [7:0] image_wdata; //data to write to image
wire [7:0] image_rgb; //image color
wire scroll; //scrolling signal
wire sel_console;
wire sel_image;
reg [7:0] cin;
always @(posedge HCLK)
if(HREADY)
begin
last_HADDR <= HADDR;
last_HWRITE <= HWRITE;
last_HSEL <= HSEL;
last_HTRANS <= HTRANS;
end
//Give time for the screen to refresh before writing
assign HREADYOUT = ~scroll;
//VGA interface: control the synchronization and color signals for a particular resolution
VGAInterface uVGAInterface (
.CLK(HCLK),
.COLOUR_IN(cin),
.cout(RGB),
.hs(HSYNC),
.vs(VSYNC),
.addrh(pixel_x),
.addrv(pixel_y)
);
//VGA console module: output the pixels in the text region
vga_console uvga_console(
.clk(HCLK),
.resetn(HRESETn),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.text_rgb(console_rgb),
.font_we(console_write),
.font_data(console_wdata),
.scroll(scroll)
);
//VGA image buffer: output the pixels in the image region
vga_image uvga_image(
.clk(HCLK),
.resetn(HRESETn),
.address(last_HADDR[15:2]),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.image_we(image_write),
.image_data(image_wdata),
.image_rgb(image_rgb)
);
assign sel_console = (last_HADDR[23:0]== 12'h000000000000);
assign sel_image = (last_HADDR[23:0] != 12'h000000000000);
//Set console write and write data
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
console_write <= 0;
console_wdata <= 0;
end
else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console)
begin
console_write <= 1'b1;
console_wdata <= HWDATA[7:0];
end
else
begin
console_write <= 1'b0;
console_wdata <= 0;
end
end
//Set image write and image write data
always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn)
begin
image_write <= 0;
image_wdata <= 0;
end
else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image)
begin
image_write <= 1'b1;
image_wdata <= HWDATA[7:0];
end
else
begin
image_write <= 1'b0;
image_wdata <= 0;
end
end
//Select the rgb color for a particular region
always @*
begin
if(!HRESETn)
cin <= 8'h00;
else
if(pixel_x[9:0]< 240 )
cin <= console_rgb ;
else
cin <= image_rgb;
end
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module GenericCounter(
CLK,
RESET,
ENABLE_IN,
TRIG_OUT,
COUNT
);
parameter COUNTER_WIDTH=4;
parameter COUNTER_MAX=4;
input CLK;
input RESET;
input ENABLE_IN;
output TRIG_OUT;
output [COUNTER_WIDTH-1:0] COUNT;
reg [COUNTER_WIDTH-1:0] counter;
reg triggerout;
always@(posedge CLK)begin
if (RESET)
counter<=0;
else begin
if (ENABLE_IN) begin
if (counter==(COUNTER_MAX))
counter<=0;
else
counter<=counter+1;
end
end
end
always@(posedge CLK)begin
if (RESET)
triggerout<=0;
else begin
if (ENABLE_IN && (counter==(COUNTER_MAX)))
triggerout<=1;
else
triggerout<=0;
end
end
assign COUNT=counter;
assign TRIG_OUT=triggerout;
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module dual_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [ADDR_WIDTH-1:0] addr_b,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a,
output wire [DATA_WIDTH-1:0] dout_b
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_a_reg;
reg [ADDR_WIDTH-1:0] addr_b_reg;
always @ (posedge clk)
begin
if(we)
ram[addr_a] <= din_a;
addr_a_reg <= addr_a;
addr_b_reg <= addr_b;
end
assign dout_a = ram[addr_a_reg];
assign dout_b = ram[addr_b_reg];
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module vga_console(
input wire clk,
input wire resetn,
input wire [9:0] pixel_x,
input wire [9:0] pixel_y,
input wire font_we, //font write
input wire [7:0] font_data, //input 7-bit ascii value
output reg [7:0] text_rgb, //output color
output reg scroll //signals scrolling
);
//Screen tile parameters
localparam MAX_X = 30; //Number of horizontal tiles
localparam MAX_Y = 30; //Number of tile rows
//Font ROM
wire [10:0] rom_addr;
wire [6:0] char_addr;
wire [3:0] row_addr;
wire [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit;
//Dual port RAM
wire [11:0] addr_r;
wire [11:0] addr_w;
wire [6:0] din;
wire [6:0] dout;
//Cursor
reg [6:0] cur_x_reg;
wire [6:0] cur_x_next;
reg [4:0] cur_y_reg;
wire [4:0] cur_y_next;
// wire cursor_on;
//pixel buffers
reg [9:0] pixel_x1;
reg [9:0] pixel_x2;
reg [9:0] pixel_y1;
reg [9:0] pixel_y2;
wire [7:0] font_rgb; //color for text
wire [7:0] font_inv_rgb; //color for text with cursor on top
reg current_state;
reg next_state;
wire return_key; //carriage return or '\n'
wire new_line; //move cursor to next line
//reg scroll;
reg scroll_next;
reg [4:0] yn; //row count
reg [4:0] yn_next;
reg [6:0] xn; //horizontal count
reg [6:0] xn_next;
//Module Instantiation
font_rom ufont_rom(
.clk(clk),
.addr(rom_addr),
.data(font_word)
);
dual_port_ram_sync
#(.ADDR_WIDTH(12), .DATA_WIDTH(7))
uvideo_ram
( .clk(clk),
.we(we),
.addr_a(addr_w),
.addr_b(addr_r),
.din_a(din),
.dout_a(),
.dout_b(dout)
);
//State Machine for cursor and pixel buffer
always @ (posedge clk, negedge resetn)
begin
if(!resetn)
begin
cur_x_reg <= 0;
cur_y_reg <= 0;
end
else
begin
cur_x_reg <= cur_x_next;
cur_y_reg <= cur_y_next;
pixel_x1 <= pixel_x;
pixel_x2 <= pixel_x1;
pixel_y1 <= pixel_y;
pixel_y2 <= pixel_y1;
end
end
//Font ROM Access
assign row_addr = pixel_y[3:0]; //row value
assign rom_addr = {char_addr,row_addr}; //ascii value and row of character
assign bit_addr = pixel_x2[2:0]; //delayed
assign font_bit = font_word[~bit_addr]; //output from font rom
//Return key found
assign return_key = (din == 6'b001101 || din == 6'b001010) && ~scroll; // Return || "\n"
//Backspace
assign back_space = (din == 6'b001000);
//New line logic
assign new_line = font_we && ((cur_x_reg == MAX_X-1) || return_key);
//Next Cursor Position logic
assign cur_x_next = (new_line) ? 2 :
(back_space && cur_x_reg) ? cur_x_reg - 1 :
(font_we && ~back_space && ~scroll) ? cur_x_reg + 1 : cur_x_reg;
assign cur_y_next = (cur_y_reg == MAX_Y-1) ? cur_y_reg :
((new_line) ? cur_y_reg + 1 : cur_y_reg );
//Color Generation
assign font_rgb = (font_bit) ? 8'b00011100 : 8'b00000000; //green:black
assign font_inv_rgb = (font_bit) ? 8'b0000000 : 8'b00011100; //black:green
//Display logic for cursor
// assign cursor_on = (pixel_x2[9:3] == cur_x_reg) && (pixel_y2[8:4] == cur_y_reg);
//RAM Write Enable
assign we = font_we || scroll;
//Display combinational logic
always @*
begin
text_rgb = font_rgb;
end
//Console state machine
always @(posedge clk, negedge resetn)
if(!resetn)
begin
scroll <= 1'b0;
yn <= 5'b00000;
xn <= 7'b0000000;
current_state <= 1'b0;
end
else
begin
scroll <= scroll_next;
yn <= yn_next;
xn <= xn_next;
current_state <= next_state;
end
//Console next state logic
always @*
begin
scroll_next = scroll;
xn_next = xn;
yn_next = yn;
next_state = current_state;
case(current_state)
1'b0: //Waits for a new line and the cursor on the last line of the screen
if(new_line && (cur_y_reg == MAX_Y-1))
begin
scroll_next = 1'b1;
next_state = 1'b1;
yn_next = 0;
xn_next = 7'b1111111; //Delayed by one cycle
end
else
scroll_next = 1'b0;
1'b1: //Counts through every tile and refreshes
begin
if(xn_next == MAX_X)
begin
xn_next = 7'b1111111; //Delayed by one cycle
yn_next = yn + 1'b1;
if(yn_next == MAX_Y)
begin
next_state = 1'b0;
scroll_next = 0;
end
end
else
xn_next = xn + 1'b1;
end
endcase
end
//RAM Write
assign addr_w = (scroll) ? {yn,xn} : {cur_y_reg, cur_x_reg};
assign din = (scroll) ? dout : font_data[6:0];
//RAM Read
assign addr_r =(scroll) ? {yn+1'b1,xn_next} : {pixel_y[8:4],pixel_x[9:3]};
assign char_addr = dout;
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module vga_image(
input wire clk,
input wire resetn,
input wire [9:0] pixel_x,
input wire [9:0] pixel_y,
input wire image_we,
input wire [7:0] image_data,
input wire [15:0] address,
output wire [7:0] image_rgb
);
wire [15:0] addr_r;
wire [14:0] addr_w;
wire [7:0] din;
wire [7:0] dout;
wire [9:0] img_x;
wire [9:0] img_y;
reg [15:0] address_reg;
//buffer address = bus address -1 , as the first address is used for console
always @(posedge clk)
address_reg <= address-1;
//Frame buffer
dual_port_ram_sync
#(.ADDR_WIDTH(15), .DATA_WIDTH(8))
uimage_ram
( .clk(clk),
.we(image_we),
.addr_a(addr_w),
.addr_b(addr_r),
.din_a(din),
.dout_a(),
.dout_b(dout)
);
assign addr_w = address_reg[14:0];
assign din = image_data;
assign img_x = pixel_x[9:0]-240;
assign img_y = pixel_y[9:0];
assign addr_r = {1'b0,img_y[8:2], img_x[8:2]};
assign image_rgb = dout;
endmodule

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//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module VGAInterface(
input CLK,
input [7:0] COLOUR_IN,
output reg [7:0] cout,
output reg hs,
output reg vs,
output reg [9:0] addrh,
output reg [9:0] addrv
);
// Time in Vertical Lines
parameter VertTimeToPulseWidthEnd = 10'd2;
parameter VertTimeToBackPorchEnd = 10'd31;
parameter VertTimeToDisplayTimeEnd = 10'd511;
parameter VertTimeToFrontPorchEnd = 10'd521;
// Time in Horizontal Lines
parameter HorzTimeToPulseWidthEnd = 10'd96;
parameter HorzTimeToBackPorchEnd = 10'd144;
parameter HorzTimeToDisplayTimeEnd = 10'd784;
parameter HorzTimeToFrontPorchEnd = 10'd800;
wire TrigHOut, TrigDiv;
wire [9:0] HorzCount;
wire [9:0] VertCount;
//Divide the clock frequency
GenericCounter #(.COUNTER_WIDTH(1), .COUNTER_MAX(1))
FreqDivider
(
.CLK(CLK),
.RESET(1'b0),
.ENABLE_IN(1'b1),
.TRIG_OUT(TrigDiv)
);
//Horizontal counter
GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(HorzTimeToFrontPorchEnd))
HorzAddrCounter
(
.CLK(CLK),
.RESET(1'b0),
.ENABLE_IN(TrigDiv),
.TRIG_OUT(TrigHOut),
.COUNT(HorzCount)
);
//Vertical counter
GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(VertTimeToFrontPorchEnd))
VertAddrCounter
(
.CLK(CLK),
.RESET(1'b0),
.ENABLE_IN(TrigHOut),
.COUNT(VertCount)
);
//Synchronisation signals
always@(posedge CLK) begin
if(HorzCount<HorzTimeToPulseWidthEnd)
hs <= 1'b0;
else
hs <= 1'b1;
if(VertCount<VertTimeToPulseWidthEnd)
vs <= 1'b0;
else
vs <= 1'b1;
end
//Color signals
always@(posedge CLK) begin
if ( ( (HorzCount >= HorzTimeToBackPorchEnd ) && (HorzCount < HorzTimeToDisplayTimeEnd) ) &&
( (VertCount >= VertTimeToBackPorchEnd ) && (VertCount < VertTimeToDisplayTimeEnd) ) )
cout <= COLOUR_IN;
else
cout <= 8'b00000000;
end
//output horizontal and vertical addresses
always@(posedge CLK)begin
if ((HorzCount>HorzTimeToBackPorchEnd)&&(HorzCount<HorzTimeToDisplayTimeEnd))
addrh<=HorzCount-HorzTimeToBackPorchEnd;
else
addrh<=10'b0000000000;
end
always@(posedge CLK)begin
if ((VertCount>VertTimeToBackPorchEnd)&&(VertCount<VertTimeToDisplayTimeEnd))
addrv<=VertCount-VertTimeToBackPorchEnd;
else
addrv<=10'b0000000000;
end
endmodule

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;------------------------------------------------------------------------------------------------------
; Design and Implementation of an AHB VGA peripheral and a GPIO peripheral
; 1) Input data from switches and output them to LEDs;
; 2) Display text string: "TEST" on VGA.
; 3) Change the colour of the four corners of the image region.
;------------------------------------------------------------------------------------------------------
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY ; First 32 WORDS is VECTOR TABLE
EXPORT __Vectors
__Vectors DCD 0x00003FFC
DCD Reset_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
; External Interrupts
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
GLOBAL Reset_Handler
ENTRY
; Configure the timer
LDR R1, =0x52000000 ; Timer load value register
LDR R0, =0xFFFFFFFF ; Maximum load value
STR R0, [R1]
LDR R1, =0x52000008 ; Timer control register
MOVS R0, #0x07 ; Set prescaler, reload mode, start timer
STR R0, [R1]
AGAIN
; Read from switches, and output to LEDs
LDR R1, =0x53000004 ; GPIO direction reg
MOVS R0, #00 ; Direction input
STR R0, [R1]
LDR R1, =0x53000000 ; GPIO data reg
LDR R2, [R1] ; Input data from the switch
LDR R1, =0x53000004 ; Change direction to output
MOVS R0, #01
STR R0, [R1]
LDR R1, =0x53000000 ; Output to LED
STR R2, [R1]
;Write "TEST" to the text console
LDR R1, =0x50000000
MOVS R0, #'T'
STR R0, [R1]
LDR R1, =0x50000000
MOVS R0, #'E'
STR R0, [R1]
LDR R1, =0x50000000
MOVS R0, #'S'
STR R0, [R1]
LDR R1, =0x50000000
MOVS R0, #'T'
STR R0, [R1]
;Write four white dots to four corners of the frame buffer
LDR R1, =0x50000004
LDR R0, =0xFF
STR R0, [R1]
LDR R1, =0x50000190
LDR R0, =0xFF
STR R0, [R1]
LDR R1, =0x5000EE04
LDR R0, =0xFF
STR R0, [R1]
LDR R1, =0x5000EF90
LDR R0, =0xFF
STR R0, [R1]
B AGAIN
ENDP
ALIGN 4 ; Align to a word boundary
END

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;------------------------------------------------------------------------------------------------------
; A Simple SoC Application
; Toggle LEDs at a given frequency.
;------------------------------------------------------------------------------------------------------
; Vector Table Mapped to Address 0 at Reset
PRESERVE8
THUMB
AREA RESET, DATA, READONLY ; First 32 WORDS is VECTOR TABLE
EXPORT __Vectors
__Vectors DCD 0x00003FFC ; 16K Internal Memory
DCD Reset_Handler
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
; External Interrupts
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
DCD 0
AREA |.text|, CODE, READONLY
;Reset Handler
Reset_Handler PROC
GLOBAL Reset_Handler
ENTRY
AGAIN LDR R1, =0x50000000 ;Write to LED with value 0x55
LDR R0, =0x55
STR R0, [R1]
LDR R0, =0x2FFFFF ;Delay
Loop SUBS R0,R0,#1
BNE Loop
LDR R1, =0x50000000 ;Write to LED with value 0xAA
LDR R0, =0xAA
STR R0, [R1]
LDR R0, =0x2FFFFF ;Delay
Loop1 SUBS R0,R0,#1
BNE Loop1
B AGAIN
ENDP
ALIGN 4 ; Align to a word boundary
END

31
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`timescale 1ns/1ps
module ahblite_sys_tb(
);
reg RESET, CLK;
wire [7:0] LED;
AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
initial
begin
CLK=0;
forever
begin
#5 CLK=1;
#5 CLK=0;
end
end
initial
begin
RESET=0;
#30 RESET=1;
#20 RESET=0;
end
endmodule