supleed2/ELEC70056-HSV-CW2
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Fix GPIO assertions and test-bench coverage and constraints

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This commit is contained in:
Alden0012 2022-11-14 15:28:45 +00:00
parent f2b3a72a54
commit 128a2a9eaa
2 changed files with 179 additions and 157 deletions
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30
rtl/AHB_GPIO/AHBGPIO.sv
View file

@ -97,8 +97,10 @@ module AHBGPIO
// Update input value // Update input value
always_ff @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) if(!HRESETn) begin
gpio_datain <= 16'h0000; gpio_datain <= 16'h0000;
gpio_parityerr <= '0;
end
else if (gpio_dir == 16'h0000) begin else if (gpio_dir == 16'h0000) begin
gpio_datain <= GPIOIN[15:0]; gpio_datain <= GPIOIN[15:0];
gpio_parityerr <= ~^{GPIOIN,PARITYSEL,INJECT_FAULT}; gpio_parityerr <= ~^{GPIOIN,PARITYSEL,INJECT_FAULT};
@ -119,23 +121,23 @@ module AHBGPIO
assert_gpio_write: assert property assert_gpio_write: assert property
( @(posedge HCLK) disable iff (!HRESETn) ( @(posedge HCLK) disable iff (!HRESETn)
((gpio_dir == 16'h0001) ((HADDR[7:0] == gpio_data_addr)
&& (HADDR[7:0] == gpio_data_addr)
&& HSEL && HSEL
&& HWRITE && HWRITE
&& HTRANS[1]) && HTRANS[1]
|-> (GPIOOUT[15:0] == $past(HWDATA[15:0], 1)) && HREADY) |-> ##1
(gpio_dir == 16'h0001) |-> ##1
(GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
); );
assert_gpio_read: assert property assert_gpio_read: assert property
( @(posedge HCLK) disable iff (!HRESETn) ( @(posedge HCLK) disable iff (!HRESETn)
((gpio_dir == 16'h0000) ((gpio_dir == 16'h0000)
&& (HADDR[7:0] == gpio_data_addr) && (HADDR[7:0] == gpio_data_addr)
// && HSEL // HSEL not used in Read always_ff // && HSEL // HSEL not used in Read always_ff
&& !HWRITE && !HWRITE
&& HTRANS[1]) && HTRANS[1]
|-> (HRDATA[15:0] == $past(GPIOIN[15:0], 1) && HREADY) |-> ##1
&& HREADYOUT) ((HRDATA[15:0]==$past(GPIOIN[15:0],1)) && HREADYOUT)
); );
assert_gpio_dir: assert property assert_gpio_dir: assert property
@ -143,12 +145,14 @@ module AHBGPIO
((HADDR[7:0] == gpio_dir_addr) ((HADDR[7:0] == gpio_dir_addr)
&& HSEL && HSEL
&& HWRITE && HWRITE
&& HTRANS[1]) && HTRANS[1]
|-> (gpio_dir == $past(HWDATA[15:0], 1)) && HREADY) |-> ##1
((HWDATA[7:0] == 8'h00 || HWDATA[7:0] == 8'h01)) ##1 (gpio_dir == $past(HWDATA[15:0], 1))
); );
assume_initial_valid: assume assume_initial_valid: assume property
( gpio_dir == 16'h0000 ( @(posedge HCLK)
gpio_dir == 16'h0000
|| gpio_dir == 16'h0001 || gpio_dir == 16'h0001
); );

162
tbench/ahb_gpio_tb.sv
View file

@ -11,7 +11,7 @@ interface ahb_gpio_if;
logic HCLK; logic HCLK;
logic HRESETn; logic HRESETn;
logic [31:0] HADDR; logic [31:0] HADDR;
logic [1:0] HTRANS; logic [ 1:0] HTRANS;
logic [31:0] HWDATA; logic [31:0] HWDATA;
logic HWRITE; logic HWRITE;
logic HSEL; logic HSEL;
@ -19,138 +19,149 @@ interface ahb_gpio_if;
logic HREADYOUT; logic HREADYOUT;
logic [31:0] HRDATA; logic [31:0] HRDATA;
logic [15:0] GPIOIN; logic [16:0] GPIOIN;
logic [15:0] GPIOOUT; logic [16:0] GPIOOUT;
modport DUT (input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY, GPIOIN, modport DUT
output HREADYOUT, HRDATA, GPIOOUT); ( input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY, GPIOIN,
output HREADYOUT, HRDATA, GPIOOUT
);
modport TB (input HCLK, HREADYOUT, HRDATA, GPIOOUT, modport TB
output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL, GPIOIN); ( input HCLK, HREADYOUT, HRDATA, GPIOOUT,
output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL, GPIOIN
);
endinterface endinterface
module ahb_gpio_tb;
program automatic ahb_gpio_tb
(ahb_gpio_if.TB gpioif);
localparam [7:0] gpio_data_addr = 8'h00; localparam [7:0] gpio_data_addr = 8'h00;
localparam [7:0] gpio_dir_addr = 8'h04; localparam [7:0] gpio_dir_addr = 8'h04;
localparam max_test_count = 1000; localparam max_test_count = 1000;
logic parity_sel = '0;
integer test_count; integer test_count;
class gpio_stimulus; ahb_gpio_if gpioif();
typedef enum bit[1:0] { AHBGPIO gpio(
GPIO_WRITE = 2'b00, .HCLK (gpioif.HCLK),
GPIO_READ = 2'b01, .HRESETn (gpioif.HRESETn),
GPIO_DIR = 2'b10, .HADDR (gpioif.HADDR),
RANDOM = 2'b11 .HTRANS (gpioif.HTRANS),
} stimulus_op; .HWDATA (gpioif.HWDATA),
rand stimulus_op gpio_op; .HWRITE (gpioif.HWRITE),
.HSEL (gpioif.HSEL),
.HREADY (gpioif.HREADY),
.GPIOIN (gpioif.GPIOIN),
.PARITYSEL (parity_sel),
.INJECT_FAULT ('0),
.HREADYOUT (gpioif.HREADYOUT),
.HRDATA (gpioif.HRDATA),
.GPIOOUT (gpioif.GPIOOUT),
.PARITYERR ()
);
class gpio_stimulus;
rand logic HSEL; rand logic HSEL;
rand logic HWRITE; rand logic HWRITE;
rand logic HREADY; rand logic HREADY;
rand logic [1:0] HTRANS; rand logic [ 1:0] HTRANS;
rand logic [31:0] HWDATA; rand logic [31:0] HWDATA;
rand logic [31:0] HADDR; rand logic [31:0] HADDR;
rand logic [16:0] GPIOIN;
rand logic [15:0] GPIOIN; logic [31:0] prev_haddr = '0;
constraint c_haddr {((gpio_op == GPIO_WRITE) && (HADDR == gpio_data_addr)) ||
((gpio_op == GPIO_DIR) && (HADDR == gpio_dir_addr)) ||
(gpio_op == GPIO_READ) ||
(gpio_op == RANDOM);}
constraint c_write {((gpio_op == GPIO_WRITE)|| (gpio_op == GPIO_DIR)) -> (HSEL && HWRITE && HREADY && (HTRANS == 2'b10));} constraint c_hsel
{ HSEL dist { 1 :=99, 0:=1 }; }
constraint c_hready
{ HREADY dist { 1 :=99, 0:=1 }; }
constraint c_htrans
{ HTRANS dist { 2'b10 :=90, HTRANS :=10};}
constraint c_haddr
{ HSEL -> HADDR dist {gpio_data_addr:=40, gpio_dir_addr:=40, HADDR:=20};}
constraint c_gpio_dir_write
{
(prev_haddr[7:0]==gpio_dir_addr) -> (HWDATA==32'h0000 || HWDATA ==32'h0001);
}
constraint c_gpioin_parity
{ GPIOIN[16] == ~^{GPIOIN[15:0],parity_sel};}
constraint c_read {(gpio_op == GPIO_READ) -> (HSEL && !HWRITE && HREADY);} function void post_randomize;
prev_haddr = HADDR;
endfunction
endclass endclass
gpio_stimulus stimulus_vals; gpio_stimulus stimulus_vals;
covergroup cover_addr_values; covergroup cover_ahb_transaction_vals;
coverpoint gpioif.HADDR { cp_hsel: coverpoint gpioif.HSEL{
bins hi = {1};
bins lo = {0};
}
cp_hready: coverpoint gpioif.HREADY{
bins hi = {1};
bins lo = {0};
}
cp_hwrite: coverpoint gpioif.HWRITE{
bins write = {1};
bins read = {0};
}
cp_haddr: coverpoint gpioif.HADDR {
bins data_addr = {gpio_data_addr}; bins data_addr = {gpio_data_addr};
bins dir_addr = {gpio_dir_addr}; bins dir_addr = {gpio_dir_addr};
bins invalid_addr = default; bins invalid_addr = default;
} }
endgroup cp_ahb_transaction: cross cp_hsel, cp_hready, cp_hwrite, cp_haddr {
bins ahb_write = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==1 && cp_haddr==gpio_data_addr);
covergroup cover_wr_vals; bins ahb_read = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==0);
coverpoint {HSEL,HWRITE,HREADY} { bins ahb_dir = cp_ahb_transaction with (cp_hsel==1 && cp_hready==1 && cp_hwrite==1 && cp_haddr==gpio_dir_addr);
bins write = {{1,1,1}}; ignore_bins ignore_invalid = cp_ahb_transaction with (cp_hsel!=1);
bins read = {{1,0,1}};
bins invalid = default;
} }
endgroup endgroup
covergroup cover_ahb_write_values; covergroup cover_ahb_write_values;
coverpoint gpioif.HWDATA { coverpoint gpioif.HWDATA;
bins zero = {0};
bins lo = {[1:7]};
bins med = {[8:23]};
bins hi = {[24:30]};
bins max = {32'hFFFF};
}
endgroup endgroup
covergroup cover_ahb_read_values; covergroup cover_ahb_read_values;
coverpoint gpioif.HRDATA { coverpoint gpioif.HRDATA;
bins zero = {0};
bins lo = {[1:7]};
bins med = {[8:23]};
bins hi = {[24:30]};
bins max = {32'hFFFF};
}
endgroup endgroup
covergroup cover_gpio_in_values; covergroup cover_gpio_in_values;
coverpoint gpioif.GPIOIN { coverpoint gpioif.GPIOIN;
bins zero = {0};
bins lo = {[1:4]};
bins med = {[5:9]};
bins high = {[10:14]};
bins max = {16'hFF};
}
endgroup endgroup
covergroup cover_gpio_out_values; covergroup cover_gpio_out_values;
coverpoint gpioif.GPIOOUT { coverpoint gpioif.GPIOOUT;
bins zero = {0};
bins lo = {[1:4]};
bins med = {[5:9]};
bins high = {[10:14]};
bins max = {16'hFF};
}
endgroup endgroup
task deassert_reset(); task deassert_reset();
begin begin
gpioif.HRESETn = 0; gpioif.HRESETn = 0;
@(posedge gpioif.HCLK); @(posedge gpioif.HCLK);
@(posedge gpioif.HCLK); @(posedge gpioif.HCLK);
gpioif.HRESETn = 1; gpioif.HRESETn = 1;
@(posedge gpioif.HCLK);
end end
endtask endtask
initial begin initial begin
cover_addr_values covaddr;
cover_ahb_write_values covahbwrite; cover_ahb_write_values covahbwrite;
cover_ahb_read_values covahbread; cover_ahb_read_values covahbread;
cover_gpio_in_values covgpioin; cover_gpio_in_values covgpioin;
cover_gpio_out_values covgpioout; cover_gpio_out_values covgpioout;
covaddr = new(); cover_ahb_transaction_vals covahbtransactionvals;
covahbwrite = new(); covahbwrite = new();
covahbread = new(); covahbread = new();
covgpioin = new(); covgpioin = new();
covgpioout = new(); covgpioout = new();
covahbtransactionvals = new();
stimulus_vals = new();
deassert_reset(); deassert_reset();
for(test_count = 0; test_count < max_test_count;test_count++) for(test_count = 0; test_count < max_test_count;test_count++)
begin begin
@(posedge gpioif.HCLK);
assert (stimulus_vals.randomize) else $fatal; assert (stimulus_vals.randomize) else $fatal;
gpioif.HSEL = stimulus_vals.HSEL; gpioif.HSEL = stimulus_vals.HSEL;
gpioif.HWRITE = stimulus_vals.HWRITE; gpioif.HWRITE = stimulus_vals.HWRITE;
@ -160,13 +171,20 @@ program automatic ahb_gpio_tb
gpioif.HADDR = stimulus_vals.HADDR; gpioif.HADDR = stimulus_vals.HADDR;
gpioif.GPIOIN = stimulus_vals.GPIOIN; gpioif.GPIOIN = stimulus_vals.GPIOIN;
covaddr.sample();
covahbwrite.sample(); covahbwrite.sample();
covgpioin.sample(); covgpioin.sample();
covahbread.sample(); covahbread.sample();
covgpioout.sample(); covgpioout.sample();
covahbtransactionvals.sample();
@(posedge gpioif.HCLK);
end end
@(posedge gpioif.HCLK); @(posedge gpioif.HCLK);
$finish; $finish;
end end
endprogram initial begin
gpioif.HCLK = 0;
forever #1 gpioif.HCLK = ! gpioif.HCLK;
end
endmodule