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Add assertions to AHBGPIO.sv

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Alden0012 2022-11-08 17:04:59 +00:00
parent 0d4099ce15
commit 0f8578e1b8
1 changed files with 57 additions and 20 deletions
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77
rtl/AHB_GPIO/AHBGPIO.sv
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@ -36,22 +36,22 @@
module AHBGPIO module AHBGPIO
( input wire HCLK ( input wire HCLK
, input wire HRESETn , input wire HRESETn
, input wire [31:0] HADDR , input wire [31:0] HADDR
, input wire [1:0] HTRANS , input wire [ 1:0] HTRANS
, input wire [31:0] HWDATA , input wire [31:0] HWDATA
, input wire HWRITE , input wire HWRITE
, input wire HSEL , input wire HSEL
, input wire HREADY , input wire HREADY
, input wire [16:0] GPIOIN , input wire [16:0] GPIOIN
, input wire PARITYSEL , input wire PARITYSEL
, input wire INJECT_FAULT , input wire INJECT_FAULT
//Output //Output
, output wire HREADYOUT , output wire HREADYOUT
, output wire [31:0] HRDATA , output wire [31:0] HRDATA
, output wire [16:0] GPIOOUT , output wire [16:0] GPIOOUT
, output wire PARITYERR , output wire PARITYERR
); );
localparam [7:0] gpio_data_addr = 8'h00; localparam [7:0] gpio_data_addr = 8'h00;
@ -64,16 +64,16 @@ module AHBGPIO
reg [15:0] gpio_dir; reg [15:0] gpio_dir;
reg [15:0] gpio_data_next; reg [15:0] gpio_data_next;
reg [31:0] last_HADDR; reg [31:0] last_HADDR;
reg [1:0] last_HTRANS; reg [ 1:0] last_HTRANS;
reg last_HWRITE; reg last_HWRITE;
reg last_HSEL; reg last_HSEL;
integer i; integer i;
assign HREADYOUT = 1'b1; assign HREADYOUT = 1'b1;
// Set Registers from address phase // Set Registers from address phase
always @(posedge HCLK) always_ff @(posedge HCLK)
if(HREADY) begin if(HREADY) begin
last_HADDR <= HADDR; last_HADDR <= HADDR;
last_HTRANS <= HTRANS; last_HTRANS <= HTRANS;
@ -82,14 +82,14 @@ module AHBGPIO
end end
// Update in/out switch // Update in/out switch
always @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) if(!HRESETn)
gpio_dir <= 16'h0000; gpio_dir <= 16'h0000;
else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dir <= HWDATA[15:0]; gpio_dir <= HWDATA[15:0];
// Update output value // Update output value
always @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) if(!HRESETn)
{gpio_parityout, gpio_dataout} <= 17'd0; {gpio_parityout, gpio_dataout} <= 17'd0;
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) begin else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) begin
@ -98,7 +98,7 @@ module AHBGPIO
end end
// Update input value // Update input value
always @(posedge HCLK, negedge HRESETn) always_ff @(posedge HCLK, negedge HRESETn)
if(!HRESETn) if(!HRESETn)
gpio_datain <= 16'h0000; gpio_datain <= 16'h0000;
else if (gpio_dir == 16'h0000) begin else if (gpio_dir == 16'h0000) begin
@ -112,4 +112,41 @@ module AHBGPIO
assign GPIOOUT = {gpio_parityout, gpio_dataout}; assign GPIOOUT = {gpio_parityout, gpio_dataout};
assign PARITYERR = gpio_parityerr; assign PARITYERR = gpio_parityerr;
//check behaviour
assert_parity: assert property
( @posedge(HCLK) disable iff (!HRESETn)
!PARITYERR;
);
assert_gpio_write: assert property
( @posedge(HCLK) disable iff (!HRESETn)
((gpio_dir == 16'h0001)
&& (HADDR[7:0] == gpio_data_addr)
&& HSEL
&& HWRITE
&& HTRANS[1])
|-> (GPIOOUT[15:0] == $past(HWDATA[15:0], 1))
);
assert_gpio_read: assert property
( @posedge(HCLK) disable iff (!HRESETn)
((gpio_dir == 16'h0000)
&& (HADDR[7:0] == gpio_data_addr)
// && HSEL // HSEL not used in Read always_ff
&& !HWRITE
&& HTRANS[1])
|-> (HRDATA[15:0] == $past(GPIOIN[15:0], 1)
&& HREADYOUT)
);
assert_gpio_dir: assert property
( @posedge(HCLK) disable iff (!HRESETn)
((HADDR[7:0] == gpio_dir_addr)
&& HSEL
&& HWRITE
&& HTRANS[1])
|-> (gpio_dir == $past(HWDATA[15:0], 1))
);
endmodule endmodule