mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
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90 lines
3.9 KiB
Systemverilog
90 lines
3.9 KiB
Systemverilog
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//////////////////////////////////////////////////////////////////////////////////
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//END USER LICENCE AGREEMENT //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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//THIS END USER LICENCE AGREEMENT (<28>LICENCE<43>) IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
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//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
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//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
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//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
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// //
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//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
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//a non-exclusive, worldwide, non-transferable, copyright licence only to //
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//redistribute and use in source and binary forms, with or without modification,//
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//for academic purposes provided the following conditions are met: //
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//a) Redistributions of source code must retain the above copyright notice, this//
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//list of conditions and the following disclaimer. //
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//b) Redistributions in binary form must reproduce the above copyright notice, //
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//this list of conditions and the following disclaimer in the documentation //
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//and/or other materials provided with the distribution. //
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// //
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//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
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//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
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//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
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//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
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//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
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//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
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//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
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//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
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//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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module vga_image(
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input wire clk,
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input wire resetn,
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input wire [9:0] pixel_x,
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input wire [9:0] pixel_y,
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input wire image_we,
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input wire [7:0] image_data,
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input wire [15:0] address,
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output wire [7:0] image_rgb
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);
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wire [15:0] addr_r;
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wire [14:0] addr_w;
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wire [7:0] din;
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wire [7:0] dout;
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wire [9:0] img_x;
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wire [9:0] img_y;
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reg [15:0] address_reg;
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//buffer address = bus address -1 , as the first address is used for console
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always @(posedge clk)
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address_reg <= address-1;
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//Frame buffer
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dual_port_ram_sync
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#(.ADDR_WIDTH(15), .DATA_WIDTH(8))
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uimage_ram
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( .clk(clk),
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.we(image_we),
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.addr_a(addr_w),
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.addr_b(addr_r),
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.din_a(din),
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.dout_a(),
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.dout_b(dout)
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);
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assign addr_w = address_reg[14:0];
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assign din = image_data;
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assign img_x = pixel_x[9:0]-240;
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assign img_y = pixel_y[9:0];
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assign addr_r = {1'b0,img_y[8:2], img_x[8:2]};
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assign image_rgb = dout;
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endmodule
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