ELEC70056-HSV-CW2/tbench/ahblite_sys_tb.sv

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2022-11-07 12:41:05 +00:00
`timescale 1ns/1ps
module ahblite_sys_tb(
);
reg RESET, CLK;
wire [7:0] LED;
AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
// Note: you can modify this to give a 50MHz clock or whatever is appropriate
initial
begin
CLK=0;
forever
begin
#5 CLK=1;
#5 CLK=0;
end
end
initial
begin
RESET=0;
#30 RESET=1;
#20 RESET=0;
end
endmodule