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135 lines
5.9 KiB
Systemverilog
135 lines
5.9 KiB
Systemverilog
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//////////////////////////////////////////////////////////////////////////////////
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//END USER LICENCE AGREEMENT //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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//THIS END USER LICENCE AGREEMENT (<28>LICENCE<43>) IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
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//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
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//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
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//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
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// //
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//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
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//a non-exclusive, worldwide, non-transferable, copyright licence only to //
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//redistribute and use in source and binary forms, with or without modification,//
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//for academic purposes provided the following conditions are met: //
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//a) Redistributions of source code must retain the above copyright notice, this//
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//list of conditions and the following disclaimer. //
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//b) Redistributions in binary form must reproduce the above copyright notice, //
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//this list of conditions and the following disclaimer in the documentation //
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//and/or other materials provided with the distribution. //
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// //
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//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
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//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
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//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
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//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
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//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
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//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
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//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
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//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
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//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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module AHBDCD(
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input wire [31:0] HADDR,
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output wire HSEL_S0,
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output wire HSEL_S1,
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output wire HSEL_S2,
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output wire HSEL_S3,
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output wire HSEL_S4,
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output wire HSEL_S5,
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output wire HSEL_S6,
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output wire HSEL_S7,
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output wire HSEL_S8,
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output wire HSEL_S9,
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output wire HSEL_NOMAP,
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output reg [3:0] MUX_SEL
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);
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reg [15:0] dec;
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//REFER CM0-DS REFERENC MANUAL FOR RAM & PERIPHERAL MEMORY MAP
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// //MEMORY MAP --> START ADDR END ADDR SIZE
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assign HSEL_S0 = dec[0]; //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MB
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assign HSEL_S1 = dec[1]; //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MB
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assign HSEL_S2 = dec[2]; //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MB
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assign HSEL_S3 = dec[3]; //MEMORY MAP --> 0x5200_0000 to 0x52FF_FFFF 16MB
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assign HSEL_S4 = dec[4]; //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MB
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assign HSEL_S5 = dec[5]; //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MB
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assign HSEL_S6 = dec[6]; //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MB
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assign HSEL_S7 = dec[7]; //MEMORY MAP --> 0x5600_0000 to 0x56FF_FFFF 16MB
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assign HSEL_S8 = dec[8]; //MEMORY MAP --> 0x5700_0000 to 0x57FF_FFFF 16MB
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assign HSEL_S9 = dec[9]; //MEMORY MAP --> 0x5800_0000 to 0x58FF_FFFF 16MB
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assign HSEL_NOMAP = dec[15]; //REST OF REGION NOT COVERED ABOVE
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always@*
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begin
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case(HADDR[31:24])
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8'h00: //MEMORY MAP --> 0x0000_0000 to 0x00FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_00000001;
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MUX_SEL = 4'b0000;
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end
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8'h50: //MEMORY MAP --> 0x5000_0000 to 0x50FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_0000_0010;
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MUX_SEL = 4'b0001;
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end
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8'h51: //MEMORY MAP --> 0x5100_0000 to 0x51FF_FFFF 16MB
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begin
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dec =16'b0000_0000_0000_0100;
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MUX_SEL = 4'b0010;
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end
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8'h52: //MEMORY MAP --> 0x5200_0000 to 0x52FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_0000_1000;
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MUX_SEL = 4'b0011;
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end
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8'h53: //MEMORY MAP --> 0x5300_0000 to 0x53FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_0001_0000;
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MUX_SEL = 4'b0100;
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end
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8'h54: //MEMORY MAP --> 0x5400_0000 to 0x54FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_0010_0000;
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MUX_SEL = 4'b0101;
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end
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8'h55: //MEMORY MAP --> 0x5500_0000 to 0x55FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_0100_0000;
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MUX_SEL = 4'b0110;
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end
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8'h56: //MEMORY MAP --> 0x5600_0000 to 0x56FF_FFFF 16MB
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begin
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dec = 16'b0000_0000_1000_0000;
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MUX_SEL = 4'b0111;
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end
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8'h57: //MEMORY MAP --> 0x5700_0000 to 0x57FF_FFFF 16MB
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begin
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dec = 16'b0000_0001_0000_0000;
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MUX_SEL = 4'b1000;
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end
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8'h58: //MEMORY MAP --> 0x5800_0000 to 0x58FF_FFFF 16MB
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begin
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dec = 16'b0000_0010_0000_0000;
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MUX_SEL = 4'b1001;
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end
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default: //NOMAP
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begin
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dec = 16'b1000_0000_00000000;
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MUX_SEL = 4'b1111;
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end
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endcase
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end
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endmodule
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