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32 lines
376 B
Systemverilog
32 lines
376 B
Systemverilog
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`timescale 1ns/1ps
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module ahblite_sys_tb(
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);
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reg RESET, CLK;
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wire [7:0] LED;
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AHBLITE_SYS dut(.CLK(CLK), .RESET(RESET), .LED(LED));
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// Note: you can modify this to give a 50MHz clock or whatever is appropriate
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initial
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begin
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CLK=0;
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forever
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begin
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#5 CLK=1;
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#5 CLK=0;
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end
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end
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initial
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begin
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RESET=0;
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#30 RESET=1;
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#20 RESET=0;
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end
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endmodule
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