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204 lines
6.9 KiB
Plaintext
204 lines
6.9 KiB
Plaintext
theory HSV_tasks_2019_solutions_task11 imports Main begin
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section \<open>Representation of circuits.\<close>
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text \<open>A wire is represented as an integer.\<close>
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type_synonym wire = int
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datatype gate =
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NOT "wire" "wire"
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| AND "wire" "wire" "wire"
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| OR "wire" "wire" "wire"
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| TRUE "wire"
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| FALSE "wire"
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text \<open>A circuit is represented as a list gates together with a list of output wires.\<close>
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type_synonym circuit = "gate list \<times> wire list"
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text \<open>Here are some examples of circuits.\<close>
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definition "circuit1 == ([NOT 1 2], [2])"
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definition "circuit2 == ([NOT 1 3, NOT 2 4, AND 3 4 5, NOT 5 6], [6])"
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definition "circuit3 == ([NOT 1 3, NOT 2 4, NOT 1 7, AND 3 4 5, NOT 5 6], [6])"
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definition "circuit4 == ([NOT 1 3, NOT 2 4, NOT 1 7, NOT 7 8, AND 3 4 5, NOT 5 6], [6])"
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text \<open>Return the input wire(s) of a gate.\<close>
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fun inputs_of where
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"inputs_of (NOT wi _) = {wi}"
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| "inputs_of (AND wi1 wi2 _) = {wi1, wi2}"
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| "inputs_of (OR wi1 wi2 _) = {wi1, wi2}"
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| "inputs_of (TRUE _) = {}"
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| "inputs_of (FALSE _) = {}"
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text \<open>Return the output wire of a gate.\<close>
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fun output_of where
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"output_of (NOT _ wo) = wo"
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| "output_of (AND _ _ wo) = wo"
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| "output_of (OR _ _ wo) = wo"
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| "output_of (TRUE wo) = wo"
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| "output_of (FALSE wo) = wo"
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section \<open>Evaluating circuits.\<close>
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text \<open>A valuation associates every wire with a truth-value.\<close>
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type_synonym valuation = "wire \<Rightarrow> bool"
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text \<open>A few examples of valuations.\<close>
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definition "\<rho>0 == \<lambda>_. True"
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definition "\<rho>1 == \<rho>0(1 := True, 2 := False, 3 := True)"
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definition "\<rho>2 == \<rho>0(1 := True, 2 := True, 3 := True)"
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text \<open>Calculate the output of a single gate, given a valuation.\<close>
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fun sim_gate :: "valuation \<Rightarrow> gate \<Rightarrow> bool" where
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"sim_gate \<rho> (NOT wi wo) = (\<not> \<rho> wi)"
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| "sim_gate \<rho> (AND wi1 wi2 wo) = (\<rho> wi1 \<and> \<rho> wi2)"
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| "sim_gate \<rho> (OR wi1 wi2 wo) = (\<rho> wi1 \<or> \<rho> wi2)"
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| "sim_gate \<rho> (TRUE wo) = True"
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| "sim_gate \<rho> (FALSE wo) = False"
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text \<open>Simulates a list of gates, given an initial valuation. Produces a new valuation.\<close>
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fun sim_gates :: "valuation \<Rightarrow> gate list \<Rightarrow> valuation" where
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"sim_gates \<rho> [] = \<rho>"
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| "sim_gates \<rho> (g # gs) = sim_gates (\<rho> (output_of g := sim_gate \<rho> g)) gs"
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text \<open>Simulates a circuit, given an initial valuation. Produces a list of
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truth-values, one truth-value per output.\<close>
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fun sim :: "valuation \<Rightarrow> circuit \<Rightarrow> bool list" where
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"sim \<rho> (gs, wos) = map (sim_gates \<rho> gs) wos"
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text \<open>Testing the simulator.\<close>
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value "sim \<rho>1 circuit1"
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value "sim \<rho>2 circuit1"
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value "sim \<rho>1 circuit2"
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value "sim \<rho>2 circuit2"
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value "sim \<rho>1 circuit3"
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value "sim \<rho>2 circuit3"
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section \<open>Optimising circuits by removing dead gates.\<close>
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text \<open>Return the set of wires that lead to an output.\<close>
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fun live_wires where
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"live_wires ([], wos) = set wos"
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| "live_wires (g # gs, wos) = (let ws = live_wires (gs, wos) in
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(if output_of g \<in> ws then inputs_of g else {}) \<union> ws)"
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value "live_wires ([NOT 1 3, NOT 2 4, NOT 1 7, AND 3 4 5, NOT 5 6], [6])"
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value "live_wires ([NOT 1 3, NOT 2 4, NOT 1 7, NOT 7 8, AND 3 4 5, NOT 5 6], [6])"
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value "live_wires ([NOT 1 3, NOT 2 4, NOT 1 7, NOT 7 8, AND 3 4 5, NOT 5 6], [6, 8])"
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value "live_wires ([NOT 1 3, NOT 2 4, NOT 7 8, AND 3 4 5, NOT 5 6], [6])"
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text \<open>This is a helper function for the next function .\<close>
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fun remove_dead_inner where
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"remove_dead_inner [] wos = []"
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| "remove_dead_inner (g # gs) wos =
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(let gs' = remove_dead_inner gs wos in
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(if output_of g \<in> live_wires (gs', wos) then [g] else []) @ gs')"
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text \<open>This function strips out gates that are not needed.\<close>
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fun remove_dead where
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"remove_dead (gs, wos) = (remove_dead_inner gs wos, wos)"
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value "remove_dead circuit2"
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value "remove_dead circuit3"
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value "remove_dead circuit4"
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section \<open>Proving that removing dead gates does not change a circuit's behaviour.\<close>
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text \<open>This lemma is obviously false -- it wrongly claims that remove_dead
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has no effect on a circuit.\<close>
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lemma "remove_dead c = c" oops
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text \<open>We shall say that two functions are 'congruent on X' if they coincide on all inputs in X.\<close>
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fun cong_on where
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"cong_on X f g = (\<forall>x \<in> X. f x = g x)"
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text \<open>Congruency is transitive.\<close>
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lemma cong_on_trans:
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assumes "cong_on X g h"
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assumes "cong_on X f g"
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shows "cong_on X f h"
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using assms by simp
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text \<open>This is a rather technical lemma. It says that if two valuations \<rho> and \<rho>' are
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congruent on all wires that are live in circuit (g # gs, wos), then the
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respective valuations obtained after simulating g remain congruent on all wires
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that are live in circuit (gs, wos). \<close>
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lemma cong_on_live_wires:
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assumes "cong_on (live_wires (g # gs, wos)) \<rho> \<rho>'"
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shows "cong_on (live_wires (gs, wos)) (\<rho>(output_of g := sim_gate \<rho> g)) (\<rho>'(output_of g := sim_gate \<rho>' g))"
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using assms
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apply (cases "output_of g \<in> live_wires (gs, wos)", auto)
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apply (cases g, auto)+
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done
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text \<open>If valuations \<rho> and \<rho>' are congruent on all wires that are live in circuit (gs, wos), then
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the respective valuations obtained after simulating gs are congruent on all wires in wos.\<close>
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lemma cong_sim_gates:
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assumes "cong_on (live_wires (gs, wos)) \<rho> \<rho>'"
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shows "cong_on (set wos) (sim_gates \<rho> gs) (sim_gates \<rho>' gs)"
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using assms
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proof (induct gs arbitrary: \<rho> \<rho>')
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case Nil
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thus ?case by auto
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next
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case (Cons g gs)
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show ?case
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apply (clarsimp simp del: cong_on.simps)
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apply (rule Cons.hyps[OF cong_on_live_wires[OF Cons.prems]])
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done
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qed
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text \<open>This is a slightly unwrapped version of the main theorem below.\<close>
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lemma sim_remove_dead:
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"cong_on (set wos) (sim_gates \<rho> (remove_dead_inner gs wos)) (sim_gates \<rho> gs)"
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proof (induct gs arbitrary: \<rho>)
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case Nil
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thus ?case by simp
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next
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case (Cons g gs \<rho>)
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show ?case
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proof (cases "output_of g \<in> live_wires (remove_dead (gs, wos))")
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case True
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thus ?thesis using Cons.hyps by auto
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next
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case False
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thus ?thesis
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apply (simp del: cong_on.simps)
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apply (rule cong_on_trans)
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apply (rule Cons.hyps[of "\<rho>(output_of g := sim_gate \<rho> g)"])
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apply (rule cong_sim_gates)
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apply clarsimp
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done
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qed
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qed
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text \<open>We define a convenient shorthand for expressing that two circuits have the same behaviour.\<close>
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fun sim_equiv (infix "\<sim>" 50) where
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"c1 \<sim> c2 = (\<forall>\<rho>. sim \<rho> c1 = sim \<rho> c2)"
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text \<open>Main theorem: removing the dead gates from a circuit does not change its behaviour.\<close>
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theorem "remove_dead c \<sim> c"
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using sim_remove_dead by (cases c, auto)
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end |