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Isabelle Task 4 mostly complete
Add opt_redundancy Format opt_redundancy test cases Prove opt_redundancy is sound Proof for "opt_redundancy never increases area" is incomplete
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@ -141,26 +141,308 @@ next
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qed(simp+)
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section "Task 4: More logic optimisation"
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(* Note: - opt_redundancy is shown to be valid (opt_redundancy_is_sound)
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- opt_redundancy never increases area is incomplete (opt_redundancy_never_inc_area)
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*)
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lemma (* test case *)
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"opt_redundancy (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))
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= INPUT 1"
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(* by eval *) oops
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lemma (* test case *)
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"opt_redundancy (AND (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))
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(OR (AND (INPUT 1) (OR (INPUT 1) (INPUT 2))) (INPUT 2)))
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= INPUT 1"
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(* by eval *) oops
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lemma (* test case *)
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"opt_redundancy (AND (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))
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(OR (INPUT 2) (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))))
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= INPUT 1"
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(* by eval *) oops
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lemma (* test case *)
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"opt_redundancy (AND (AND (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))
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(OR (INPUT 2) (AND (INPUT 1) (OR (INPUT 1) (INPUT 2)))))
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(OR (INPUT 1) (INPUT 2)))
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= INPUT 1"
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(* by eval *) oops
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(* An optimisation that exploits the following Boolean identities:
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`a | (a & b) = a`
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`(a & b) | a = a`
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`a & (a | b) = a`
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`(a | b) & a = a`
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*)
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fun opt_redundancy :: "circuit \<Rightarrow> circuit" where
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"opt_redundancy (NOT c) = NOT (opt_redundancy c)"
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| "opt_redundancy (OR c1 (AND c2 c3)) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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let c3' = opt_redundancy c3 in
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if (c1' = c2') | (c1' = c3') then c1'
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else if c2' = c3' then OR c1' c2'
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else OR c1' (opt_redundancy (AND c2 c3)))"
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| "opt_redundancy (OR (AND c1 c2) c3) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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let c3' = opt_redundancy c3 in
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if (c1' = c3') | (c2' = c3') then c3'
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else if c1' = c2' then OR c1' c3'
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else OR (opt_redundancy (AND c1 c2)) c3')"
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| "opt_redundancy (AND c1 (OR c2 c3)) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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let c3' = opt_redundancy c3 in
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if (c1' = c2') | (c1' = c3') then c1'
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else if c2' = c3' then AND c1' c2'
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else AND c1' (opt_redundancy (OR c2 c3)))"
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| "opt_redundancy (AND (OR c1 c2) c3) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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let c3' = opt_redundancy c3 in
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if (c1' = c3') | (c2' = c3') then c3'
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else if c1' = c2' then AND c1' c3'
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else AND (opt_redundancy (OR c1 c2)) c3')"
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| "opt_redundancy (AND c1 c2) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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if c1' = c2' then c1' else AND c1' c2')"
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| "opt_redundancy (OR c1 c2) = (
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let c1' = opt_redundancy c1 in
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let c2' = opt_redundancy c2 in
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if c1' = c2' then c1' else OR c1' c2')"
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| "opt_redundancy TRUE = TRUE"
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| "opt_redundancy FALSE = FALSE"
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| "opt_redundancy (INPUT i) = INPUT i"
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lemma "opt_redundancy (AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2))) = INPUT 1" by eval (* test case *)
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lemma "opt_redundancy (AND (AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2)))
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(OR (AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2)))
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(INPUT 2))) = INPUT 1" by eval (* test case *)
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lemma "opt_redundancy (AND (AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2)))
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(OR (INPUT 2)
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(AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2))))) = INPUT 1" by eval (* test case *)
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lemma "opt_redundancy (AND (AND (AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2)))
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(OR (INPUT 2)
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(AND (INPUT 1)
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(OR (INPUT 1)
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(INPUT 2)))))
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(OR (INPUT 1)
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(INPUT 2))) = INPUT 1" by eval (* test case *)
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theorem opt_redundancy_is_sound: "opt_redundancy c \<sim> c"
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proof (induct rule:opt_redundancy.induct)
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case (2 c1 c2 c3)
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thus ?case by (smt (verit) opt_redundancy.simps(2) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("3_1" c1 c2 v)
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thus ?case by (smt (verit) opt_redundancy.simps(3) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("3_2" c1 c2 v va)
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thus ?case by (smt (verit) opt_redundancy.simps(4) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("3_3" c1 c2)
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thus ?case by (smt (verit) opt_redundancy.simps(5) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("3_4" c1 c2)
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thus ?case by (smt (verit) opt_redundancy.simps(6) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("3_5" c1 c2 v)
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thus ?case by (smt (verit) opt_redundancy.simps(7) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case (4 c1 c2 c3)
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thus ?case by (smt (verit) opt_redundancy.simps(8) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("5_1" c1 c2 v)
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thus ?case by (smt (verit) opt_redundancy.simps(9) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("5_2" c1 c2 v va)
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thus ?case by (smt (verit) opt_redundancy.simps(10) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("5_3" c1 c2)
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thus ?case by (smt (verit) opt_redundancy.simps(11) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("5_4" c1 c2)
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thus ?case by (smt (verit) opt_redundancy.simps(12) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("5_5" c1 c2 v)
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thus ?case by (smt (verit) opt_redundancy.simps(13) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_1" va v)
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thus ?case by (smt (verit) opt_redundancy.simps(14) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_2" va vb v)
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thus ?case by (smt (verit) opt_redundancy.simps(15) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_6" vb v va)
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thus ?case by (smt (verit) opt_redundancy.simps(19) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_7" vb vc v va)
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thus ?case by (smt (verit) opt_redundancy.simps(20) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_8" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(21) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_9" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(22) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_10" vb v va)
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thus ?case by (smt (verit) opt_redundancy.simps(23) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_12" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(25) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_17" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(30) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_22" va vb v)
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thus ?case by (smt (verit) opt_redundancy.simps(35) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("6_25" va v)
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thus ?case by (smt (verit) opt_redundancy.simps(38) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_1" va v)
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thus ?case by (smt (verit) opt_redundancy.simps(39) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_2" va vb v)
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thus ?case by (smt (verit) opt_redundancy.simps(40) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_6" vb v va)
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thus ?case by (smt (verit) opt_redundancy.simps(44) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_7" vb vc v va)
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thus ?case by (smt (verit) opt_redundancy.simps(45) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_8" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(46) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_9" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(47) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_10" vb v va)
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thus ?case by (smt (verit) opt_redundancy.simps(48) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_12" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(50) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_17" v va)
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thus ?case by (smt (verit) opt_redundancy.simps(55) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_22" va vb v)
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thus ?case by (smt (verit) opt_redundancy.simps(60) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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next
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case ("7_25" va v)
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thus ?case by (smt (verit) opt_redundancy.simps(63) circuits_equiv.elims(1) simulate.simps(1) simulate.simps(2))
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qed(simp+)
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theorem opt_redundancy_never_inc_area: "area (opt_redundancy c) \<le> area c"
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proof (induct rule:opt_redundancy.induct)
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case (2 c1 c2 c3)
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(* area (opt_redundancy (OR c1 (AND c2 c3))) \<le> area (OR c1 (AND c2 c3)) *)
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let ?c1' = "opt_redundancy c1"
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let ?c2' = "opt_redundancy c2"
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let ?c3' = "opt_redundancy c3"
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from 2 have IH:"area (OR ?c1' (AND ?c2' ?c3')) \<le> area (OR c1 (AND c2 c3))" by fastforce
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have a:"(area (opt_redundancy (OR c1 (AND c2 c3))) = area ?c1')
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\<or> (area (opt_redundancy (OR c1 (AND c2 c3))) = area (OR ?c1' ?c2'))
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\<or> (area (opt_redundancy (OR c1 (AND c2 c3))) = area (OR ?c1' (opt_redundancy (AND c2 c3))))"
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by (smt opt_redundancy.simps(2))
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have b:"area ?c1' \<le> area (OR c1 (AND c2 c3))" using IH by simp
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have c:"area (OR ?c1' ?c2') \<le> area (OR c1 (AND c2 c3))" using IH by simp
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have d:"area (OR ?c1' (opt_redundancy (AND c2 c3))) \<le> area (OR c1 (AND c2 c3))" using IH sorry
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thus ?case using a b c d by metis
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next
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case ("3_1" c1 c2 v)
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thus ?case sorry
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next
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case ("3_2" c1 c2 v va)
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thus ?case sorry
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next
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case ("3_3" c1 c2)
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thus ?case sorry
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next
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case ("3_4" c1 c2)
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thus ?case sorry
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next
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case ("3_5" c1 c2 v)
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thus ?case sorry
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next
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case (4 c1 c2 c3)
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thus ?case sorry
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next
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case ("5_1" c1 c2 v)
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thus ?case sorry
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next
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case ("5_2" c1 c2 v va)
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thus ?case sorry
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next
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case ("5_3" c1 c2)
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thus ?case sorry
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next
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case ("5_4" c1 c2)
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thus ?case sorry
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next
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case ("5_5" c1 c2 v)
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thus ?case sorry
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next
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case ("6_1" va v)
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thus ?case sorry
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next
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case ("6_2" va vb v)
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thus ?case sorry
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next
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case ("6_6" vb v va)
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thus ?case sorry
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next
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case ("6_7" vb vc v va)
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thus ?case sorry
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next
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case ("6_8" v va)
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thus ?case sorry
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next
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case ("6_9" v va)
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thus ?case sorry
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next
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case ("6_10" vb v va)
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thus ?case sorry
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next
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case ("6_12" v va)
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thus ?case sorry
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next
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case ("6_17" v va)
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thus ?case sorry
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next
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case ("6_22" va vb v)
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thus ?case sorry
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next
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case ("6_25" va v)
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thus ?case sorry
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next
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case ("7_1" va v)
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thus ?case sorry
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next
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case ("7_2" va vb v)
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thus ?case sorry
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next
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case ("7_6" vb v va)
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thus ?case sorry
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next
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case ("7_7" vb vc v va)
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thus ?case sorry
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next
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case ("7_8" v va)
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thus ?case sorry
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next
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case ("7_9" v va)
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thus ?case sorry
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next
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case ("7_10" vb v va)
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thus ?case sorry
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next
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case ("7_12" v va)
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thus ?case sorry
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next
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case ("7_17" v va)
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thus ?case sorry
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next
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case ("7_22" va vb v)
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thus ?case sorry
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next
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case ("7_25" va v)
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thus ?case sorry
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qed(simp+)
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end
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