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Isabelle Task 3 complete
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@ -51,7 +51,7 @@ theorem "\<exists>n::nat.(n^6 mod 10 \<noteq> n mod 10)" by (rule exI[where x =
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section "Task 3: Logic optimisation"
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section "Task 3: Logic optimisation"
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(* Datatype for representing simple circuits. *)
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(* Datatype for representing simple circuits. *)
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datatype "circuit" =
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datatype "circuit" =
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NOT "circuit"
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NOT "circuit"
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| AND "circuit" "circuit"
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| AND "circuit" "circuit"
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| OR "circuit" "circuit"
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| OR "circuit" "circuit"
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@ -60,7 +60,7 @@ datatype "circuit" =
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| INPUT "int"
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| INPUT "int"
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(* Simulates a circuit given a valuation for each input wire. *)
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(* Simulates a circuit given a valuation for each input wire. *)
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fun simulate where
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fun simulate :: "circuit \<Rightarrow> (int \<Rightarrow> bool) \<Rightarrow> bool" where
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"simulate (AND c1 c2) \<rho> = ((simulate c1 \<rho>) \<and> (simulate c2 \<rho>))"
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"simulate (AND c1 c2) \<rho> = ((simulate c1 \<rho>) \<and> (simulate c2 \<rho>))"
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| "simulate (OR c1 c2) \<rho> = ((simulate c1 \<rho>) \<or> (simulate c2 \<rho>))"
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| "simulate (OR c1 c2) \<rho> = ((simulate c1 \<rho>) \<or> (simulate c2 \<rho>))"
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| "simulate (NOT c) \<rho> = (\<not> (simulate c \<rho>))"
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| "simulate (NOT c) \<rho> = (\<not> (simulate c \<rho>))"
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@ -76,7 +76,7 @@ fun circuits_equiv (infix "\<sim>" 50) (* the "50" indicates the operator preced
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`a | a = a`
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`a | a = a`
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`a & a = a`
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`a & a = a`
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*)
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*)
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fun opt_ident where
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fun opt_ident :: "circuit \<Rightarrow> circuit" where
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"opt_ident (NOT c) = NOT (opt_ident c)"
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"opt_ident (NOT c) = NOT (opt_ident c)"
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| "opt_ident (AND c1 c2) = (
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| "opt_ident (AND c1 c2) = (
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let c1' = opt_ident c1 in
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let c1' = opt_ident c1 in
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@ -90,12 +90,16 @@ fun opt_ident where
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| "opt_ident FALSE = FALSE"
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| "opt_ident FALSE = FALSE"
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| "opt_ident (INPUT i) = INPUT i"
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| "opt_ident (INPUT i) = INPUT i"
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lemma (* test case *)
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lemma "opt_ident (AND (INPUT 1) (OR (INPUT 1) (INPUT 1))) = INPUT 1" by eval (* test case *)
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"opt_ident (AND (INPUT 1) (OR (INPUT 1) (INPUT 1))) = INPUT 1"
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by eval
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theorem opt_ident_is_sound: "opt_ident c \<sim> c"
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theorem opt_ident_is_sound: "opt_ident c \<sim> c"
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oops
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proof (induct c)
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case (AND c1 c2)
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thus ?case by (smt circuits_equiv.simps opt_ident.simps(2) simulate.simps(1))
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next
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case (OR c1 c2)
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thus ?case by (smt circuits_equiv.simps opt_ident.simps(3) simulate.simps(2))
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qed(simp+)
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fun area :: "circuit \<Rightarrow> nat" where
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fun area :: "circuit \<Rightarrow> nat" where
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"area (NOT c) = 1 + area c"
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"area (NOT c) = 1 + area c"
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@ -103,6 +107,39 @@ fun area :: "circuit \<Rightarrow> nat" where
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| "area (OR c1 c2) = 1 + area c1 + area c2"
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| "area (OR c1 c2) = 1 + area c1 + area c2"
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| "area _ = 0"
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| "area _ = 0"
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theorem opt_ident_never_inc_area: "area (opt_ident c) \<le> area c"
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proof (induct c)
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case (AND c1 c2)
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{
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assume "opt_ident c1 = opt_ident c2"
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hence "area (opt_ident (AND c1 c2)) = area (opt_ident c1)" by simp
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hence "area (opt_ident (AND c1 c2)) \<le> area (AND (opt_ident c1) (opt_ident c2))" by simp
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hence ?case using AND.hyps(2) \<open>opt_ident c1 = opt_ident c2\<close> by auto
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}
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moreover
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{
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assume "opt_ident c1 \<noteq> opt_ident c2"
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hence "area (opt_ident (AND c1 c2)) = area (AND (opt_ident c1) (opt_ident c2))" by simp
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hence ?case by (simp add: AND.hyps(1) AND.hyps(2) add_mono_thms_linordered_semiring(1))
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}
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ultimately show ?case by fastforce
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next
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case (OR c1 c2)
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{
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assume "opt_ident c1 = opt_ident c2"
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hence "area (opt_ident (OR c1 c2)) = area (opt_ident c1)" by simp
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hence "area (opt_ident (OR c1 c2)) \<le> area (OR (opt_ident c1) (opt_ident c2))" by simp
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hence ?case using OR.hyps(2) \<open>opt_ident c1 = opt_ident c2\<close> by auto
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}
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moreover
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{
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assume "opt_ident c1 \<noteq> opt_ident c2"
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hence "area (opt_ident (OR c1 c2)) = area (OR (opt_ident c1) (opt_ident c2))" by simp
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hence ?case by (simp add: OR.hyps(1) OR.hyps(2) add_mono_thms_linordered_semiring(1))
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}
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ultimately show ?case by fastforce
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qed(simp+)
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section "Task 4: More logic optimisation"
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section "Task 4: More logic optimisation"
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lemma (* test case *)
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lemma (* test case *)
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