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199 lines
11 KiB
HTML
199 lines
11 KiB
HTML
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="utf-8" />
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<title>
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ISSIE
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</title>
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<meta name="viewport" content="width=device-width, initial-scale=1.0" />
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<meta name="description" content="Schematic Editor and Simulator" />
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<meta name="author" content="tomcl" />
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<link rel="icon" type="image/x-icon" href="content/img/icon.ico" />
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<link rel="stylesheet" href="content/style.css" />
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<!-- HTML5 shim, for IE6-8 support of HTML5 elements -->
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<!--[if lt IE 9]>
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<script src="https://oss.maxcdn.com/html5shiv/3.7.2/html5shiv.min.js"></script>
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<![endif]-->
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</head>
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<body>
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<h><a name="Home" href="index.html"></a></h>
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<div class="topnav">
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<a href="index.html" style="font-size: 30px; font-weight:bolder">ISSIE</a>
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<a href="UserGuide.html">User Guide</a>
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<a href="DeveloperInfo.html">Developer Info</a>
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<a href="https://github.com/tomcl/issie/wiki/Issie-Blog"> Issie Blog</a>
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<a href="Contact.html">Contact</a>
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<div class="topnav-right">
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<a href="Download.html">Download</a>
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</div>
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</div>
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<div class="IntroBackground">
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<div class="IntroLayer">
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<p style="font-size: 24px; margin-left: 0.5%; font-weight:bolder; color: #272838; text-align: center">
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<br><br><br> Discover, Learn & Create with the ISSIE circuit schematic editor!
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</p>
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<div class="topnav-right">
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<a href="#Info">About ISSIE</a>
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<a href="#Acknowledgements">Acknowledgements</a>
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</div>
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<br><br><br><br><br>
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</div>
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</div>
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<div class="GeneralText">
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<br><br><br>
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<div class="section"><h1><a name="Info" class="anchor" href="#Info">What is Issie?</a></h1></div>
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<p>
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Issie (Interactive Schematic Simulator and Integrated Editor) is a very easy to use and capable hierarchical block schematic based digital logic editor and simulator,
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originally made for the 1st year undergraduate Digital Electronics and Computer Architecture module at the
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Department of Electronic and Electrical Engineering, Imperial College London, by 3rd year students at the same institution.
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</p>
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<p>
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Issie has been well tested on designs with up to 15,000 schematic components. We expect it to be reasonably performant on much larger designs as well.
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The simulation speed is approximately 2000 component-clocks per ms. Thus a circuit with 1000 components would run at 2000 clocks per second. Issie
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creates fully synchronous circuits with a single clock: logic with asynchronous loops is currently not supported.
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</p>
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<p>
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Issie is coded in F# transpiled to Javascript by <a href="http://fable.io">FABLE</a>, and uses a pure F# drawing library.
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</p><br>
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<div class="section"><h1><a name="Features" class="anchor" href="#Features">Key Features</a></h1></div>
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<br>
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<div id="toc_container">
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<p class="toc_title">Contents</p>
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<ul class="toc_list">
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<li><a href="#ComponentLibrary">1 Component Library</a></li>
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<li><a href="#WireRouting">2 Wire Routing</a></li>
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<li><a href="#WidthInference">3 Width Inference</a></li>
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<li>
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<a href="#Simulation">4 Circuit Simulation</a>
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<ul>
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<li><a href="#StepSimulation">4.1 Step Simulation</a></li>
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<li><a href="#WaveformSimulation">4.2 Waveform Simulation</a></li>
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</ul>
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</li>
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<li><a href="#Verilog">5 Verilog Output</a></li>
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<li><a href="#Memory">6 Memory Editor</a></li>
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</ul>
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</div>
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<div class="section" id="halfwidth"><h2><a name="ComponentLibrary" class="anchor" href="#ComponentLibrary">Component Library</a></h2></div>
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<p>
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ISSIE has an extensive and complete library of components available in the 'Catalogue' menu.
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Components include low-level gates and flipflops as
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well as larger blocks: RAMs, ROMs, n-bit registers and adders. The lack of HDL-based combinational logic is partly filled by
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special components: Bus Select (extracts a bit-field), Bus Compare (decodes a min-term of a bus). Components defined as Verilog
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combinational logic are a likely future addition.
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</p><br>
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<p>
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Viewer components are used to (optionally) view simulation waveforms of nodes on subsheets. Wire label components allow any number of
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nodes on one design sheet to be connected without visible wires.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/catalog.png" alt="Initial circuit and Component tab" />
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</div><br>
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<div class="section" id="halfwidth"><h2><a name="WireRouting" class="anchor" href="#WireRouting">Wire Routing</a></h2></div>
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<p>
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ISSIE schematic component ports are connected using drag-and-drop: each connection represents a wire or bus.
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ISSIE has two methods of routing wires: Auto-routing and Manual-routing. Wires will all start out as Auto-routed,
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which means that the wire's path is created automatically by the program. This path will update when moving any connected components.
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ISSIE also allows for manual routing, where the user may manipulate segments of the wire as desired to make the circuit more readable. Effort has
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been put into making this functionality intuitive, with automatic reversion to auto-routing when wire topology changes, and auto-routing of
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endpoints when parts of a wire are manually routed.
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</p><br>
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<div class="section" id="halfwidth"><h2><a name="WidthInference" class="anchor" href="#WidthInference">Width Inference</a></h2></div>
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<p>
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Wires will automatically be created the correct width using a width inference algorithm.
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Wires connecting two ports of incompatible widths will be highlighted red and an error message shown, as will multiply driven wires.
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Additional sanity checks (e.g. for combinational loops, or unconnected ports) are made before simulation with errors highlighted visually.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/wireerror.png" alt="Width Inferer Error Message" />
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</div><br>
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<div class="section" id="halfwidth"><h2><a name="CircuitSimulation" class="anchor" href="#CircuitSimulation">Circuit Simulation</a></h2></div>
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<p>
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ISSIE includes two simulations in order to inspect and test circuit schematics: The step simulator, and waveform simulator.
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This allows users to visualise the information in different ways to best suit their needs and understanding.
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</p><br>
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<div class="section" id="halfwidth"><h3><a name="StepSimulation" class="anchor" href="#StepSimulation">Step Simulation</a></h3></div>
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<p>
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Step Simulation allows the user to 'step' or cycle through each clock tick, and view the current design sheet's Output and Viewer component information.
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It also allows users to view how the state changes in stateful components such as RAM.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/simulation tab.png" alt="Step simulator example" />
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</div><br>
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<div class="section" id="halfwidth"><h3><a name="WaveformSimulation" class="anchor" href="#WaveformSimulation">Waveform Simulation</a></h3></div>
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<p>
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Waveform Simulation allows the user to see the values in each selected connected circuit element (<a href="https://en.wikipedia.org/wiki/Netlist">Netlist</a>) over time as a waveform.
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The waveform simulator allows users to move waveforms up/down in the list to make the simulation more readable.
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Users may cycle through the simulator using the arrows to directly go to a specific clock cycle.
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Alternatively there is a scrollbar for the Waveform simulator that will automatically lengthen the simulation once the end is reached.
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The values in the waveform simulator can be viewed in various formats: binary, hexadecimal, unsigned decimal and signed decimal.
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The Waveform Simulator also features a draggable sidebar to partition screen space dynamically between waveforms and circuit.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/waveformsimulation.png" alt="Waveform simulator example" />
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</div><br>
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<p>
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Waveform Simulation also allows for the simulation and contents viewing of memory components such as RAM.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/wavesimramview.png" alt="Waveform simulator with RAM example" />
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</div><br>
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<div class="section" id="halfwidth"><h2><a name="Verilog" class="anchor" href="#Verilog">Verilog Output</a></h2></div>
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<p>
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Users may convert their ISSIE schematic design into a Verilog file using the 'Write design as verilog' option found in the header bar of the application.
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This allows great flexibility as ISSIE designs may be used in more complex design tools and other programs that use Verilog;
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allowing ISSIE to be used as a top-level design that can be further developed if needed. Verilog output for simulation or synthesis is documented
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as part of the Verilog write process, this includes links to a [YoSys](http://bygone.clairexen.net/yosys/download.html) workflow for synthesis on FPGAs.
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Imperial College users can download a pre-installed VM for this workflow, the VHDL output is standalone and should work with other synthesis methods.
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</p><br>
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<div class="section" id="halfwidth"><h2><a name="Memory" class="anchor" href="#Memory">Memory Editor</a></h2></div>
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<p>
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ISSIE allows users to directly edit the contents of Memory components, for more versitility and ease of use. Memory contents can also be exported and imported via .ram files.
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</p><br>
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<div class="img">
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<img src="content/img/circuit/memoryeditor.png" alt="RAM editor example" />
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</div><br>
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<br>
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<div class="section"><h1><a name="Acknowledgements" class="anchor" href="#Acknowledgements">Acknowledgements:</a></h1></div>
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<ul>
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<li>Marco Selvatici for the 8K lines of base code written for his 3rd year BEng <a href="https://github.com/MarcoSelvatici/DEflow">FYP</a></li>
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<li>Edoardo Santi for work improving Issie over Summer 2020.</li>
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<li>High Level Programming 2020 cohort for providing the base code of the draw block</li>
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<li>Jo Merrick for work improving ISSIE for her 3rd year BEng Project</li>
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<li>Dr Tom Clarke for his continued work maintaining and improving ISSIE throughout</li>
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<li>All 2020/2021 1st year undergraduate students of the EEE department, Imperial College London, for acting as unpaid beta-testers!</li>
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</ul>
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</div>
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</body>
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</html>
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