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102 lines
4.5 KiB
Forth
102 lines
4.5 KiB
Forth
module SimulatorMemoriesTests
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open CommonTypes
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open SimulatorTypes
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open CanvasStatesMemories
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open NumberHelpers
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open Helpers
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/// Tuple with: (diagramName, state, loadedComponents, number of clock ticks, inputss).
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/// Note that the inputss is a list of inputs. I.e. inputss provides an inputs
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/// for every time step. The first set of inputs will be fed before the first
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/// clock tick, then second after the second clock tick and so on. If no inputs
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/// are provided for a certain iteration, none will fed.
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type private TestCaseInput = string * CanvasState * LoadedComponent list * int * ((ComponentId * WireData) list) list
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type private IterationOutput = (SimulationIO * WireData) list // Output after every clock tick.
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type private TestCaseOutput = Result<IterationOutput list, SimulationError>
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type private TestCase = string * TestCaseInput * TestCaseOutput
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let private toWD num w = convertIntToWireData w (int64 num)
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let private makeStateMem3Input addr dataIn write =
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[ (ComponentId "81030fc6-2471-a568-160f-922709edeb2e", toWD addr 3)
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(ComponentId "266d8763-6fbf-37c2-6825-d3487153053b", toWD dataIn 4)
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(ComponentId "f0769200-24e3-5c7b-3591-c5c3711d9336", toWD write 1) ]
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let private makeStateMem3Output dataOut =
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[ (ComponentId "1f9704f9-88fc-124c-3ff8-21c36cfb7328", ComponentLabel "data-out", 4), toWD dataOut 4 ]
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let testCasesSimulatorMemories : TestCase list = [
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"Synchronous ROM connected to address and output",
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("main", stateMem1, [], 6, [
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[ (ComponentId "4f65afe9-f03c-2b97-fde9-c657ca32f246", toWD 0 2) ]
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[ (ComponentId "4f65afe9-f03c-2b97-fde9-c657ca32f246", toWD 1 2) ]
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[ (ComponentId "4f65afe9-f03c-2b97-fde9-c657ca32f246", toWD 2 2) ]
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[ (ComponentId "4f65afe9-f03c-2b97-fde9-c657ca32f246", toWD 3 2) ]
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]),
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Ok [
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 0 4 ] // Mem[0]
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 0 4 ] // Mem[0]
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 1 4 ] // Mem[1]
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 4 4 ] // Mem[2]
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 15 4 ] // Mem[3]
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 4), toWD 15 4 ] // Mem[3]
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]
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"Synchronous ROM connected to address and output. ROM is big.",
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("main", stateMem2, [], pow2(8)+1, (
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[0..pow2(8)-1] |> List.map (fun i ->
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[ (ComponentId "4f65afe9-f03c-2b97-fde9-c657ca32f246", toWD i 8) ]
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)
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)),
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Ok (
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[ [ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 8), toWD 0 8 ] ] // Mem[0]
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@
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(
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[0..pow2(8)-1] |> List.map (fun i ->
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[ (ComponentId "fbb5aa79-a471-ac24-4201-56ae39d537c6", ComponentLabel "data", 8), toWD i 8 ]
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)
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)
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)
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"RAM only writes if write flag is set",
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("main", stateMem3, [], 10, [
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makeStateMem3Input 0 1 0
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makeStateMem3Input 0 1 0
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makeStateMem3Input 0 1 1 // Turn on write flag. Set to one.
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makeStateMem3Input 0 0 1 // Set to zero.
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makeStateMem3Input 0 1 1 // Set to one.
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makeStateMem3Input 0 0 0 // Turn off write flag. Stays at one.
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makeStateMem3Input 0 0 0
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makeStateMem3Input 0 0 0
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makeStateMem3Input 0 0 0
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makeStateMem3Input 0 0 0
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]),
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Ok [
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makeStateMem3Output 0 // Mem[0], unchanged
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makeStateMem3Output 0 // Mem[0], unchanged
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makeStateMem3Output 0 // Mem[0], unchanged
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makeStateMem3Output 1 // Mem[0], set to 1
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makeStateMem3Output 0 // Mem[0], set to 0
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makeStateMem3Output 1 // Mem[0], set to 1
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makeStateMem3Output 1 // Mem[0], stays 1
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makeStateMem3Output 1 // Mem[0], stays 1
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makeStateMem3Output 1 // Mem[0], stays 1
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makeStateMem3Output 1 // Mem[0], stays 1
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]
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"RAM writes and reads all locations.",
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("main", stateMem3, [], 17,
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( [0..pow2(3)-1] |> List.map(fun i -> makeStateMem3Input i (i+1) 1) ) // Write all locations.
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@
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( [0..pow2(3)-1] |> List.map(fun i -> makeStateMem3Input i 0 0) ) // Read all locations.
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),
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Ok (
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[ makeStateMem3Output 0 ]
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@
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( [0..pow2(3)-1] |> List.map(fun i -> makeStateMem3Output <| i+1) )
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@
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( [0..pow2(3)-1] |> List.map(fun i -> makeStateMem3Output <| i+1) )
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)
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]
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