ComponentType
Namespace: global
Parent Module: CommonTypes
Union Cases
| Union Case | Description |
And
Signature:
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AsyncROM(Memory)
Signature: Memory
|
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BusSelection(OutputWidth,OutputLSBit)
Signature: int * int
|
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Custom(CustomComponentType)
Signature: CustomComponentType
|
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Demux2
Signature:
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DFF
Signature:
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DFFE
Signature:
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Input(BusWidth)
Signature: int
|
|
IOLabel
Signature:
|
|
MergeWires
Signature:
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Mux2
Signature:
|
|
Nand
Signature:
|
|
NbitsAdder(BusWidth)
Signature: int
|
|
Nor
Signature:
|
|
Not
Signature:
|
|
Or
Signature:
|
|
Output(BusWidth)
Signature: int
|
|
RAM(Memory)
Signature: Memory
|
|
Register(BusWidth)
Signature: int
|
|
RegisterE(BusWidth)
Signature: int
|
|
ROM(Memory)
Signature: Memory
|
|
SplitWire(BusWidth)
Signature: int
|
|
Xnor
Signature:
|
|
Xor
Signature:
|
|