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https://github.com/supleed2/ELEC60015-HLP-CW.git
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185 lines
6.2 KiB
Forth
185 lines
6.2 KiB
Forth
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module WidthInfererTests
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open CommonTypes
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open CanvasStates
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open CanvasStatesWithBuses
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type private WidthInfererTestCaseInput = CanvasState
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type private WidthInfererTestCaseOutput = Result<ConnectionsWidth, WidthInferError>
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type private WidhtInfererTestCase = string * WidthInfererTestCaseInput * WidthInfererTestCaseOutput
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let private testCasesWidthInfererSimple : WidhtInfererTestCase list = [
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"Two unconnected input nodes. No conections", state2,
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Ok Map.empty
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"Simple circuit with one input connected to one output", state3,
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[
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ConnectionId "conn0", Some 1
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] |> Map.ofList |> Ok
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"Simple circuit with one input connected to two outputs", state4,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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] |> Map.ofList |> Ok
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"Two inputs; one And; one output", state6,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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ConnectionId "conn2", Some 1
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] |> Map.ofList |> Ok
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"Partially connected and: missing bottom connections", state25,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn2", Some 1
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] |> Map.ofList |> Ok
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"Partially connected and: missing connection to output", state26,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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] |> Map.ofList |> Ok
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"Partially connected and: missing both input connections", state27,
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[
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ConnectionId "conn2", Some 1
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] |> Map.ofList |> Ok
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"One input and one output, connected to the state3CustomComponent", state16,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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] |> Map.ofList |> Ok
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"Nested custom components", state18,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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] |> Map.ofList |> Ok
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]
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let private testCasesWidthInfererBuses : WidhtInfererTestCase list = [
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"Two inputs connected to a MergeWires component. No other connections", stateBus1,
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[
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ConnectionId "conn0", Some 1
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ConnectionId "conn1", Some 1
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] |> Map.ofList |> Ok
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"A MergeWires connected to a SplitWire 1.", stateBus2,
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[
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ConnectionId "conn0", None
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] |> Map.ofList |> Ok
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"A MergeWires connected to a SplitWire 1 and a single-bit output node", stateBus3,
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[
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ConnectionId "conn0", None
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ConnectionId "conn1", None
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] |> Map.ofList |> Ok
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"A MergeWires connected to a SplitWire 1, with loop", stateBus4,
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[
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ConnectionId "conn0", None
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ConnectionId "conn1", None
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] |> Map.ofList |> Ok
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"All the bus components in series, properly connected. No other components", stateBus6,
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[
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ConnectionId "conn0", None
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ConnectionId "conn1", None
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ConnectionId "conn2", None
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ConnectionId "conn3", None
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ConnectionId "conn4", None
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] |> Map.ofList |> Ok
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"Non-inferrable loop", stateBus7,
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[
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ConnectionId "conn0", None
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ConnectionId "conn1", None
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] |> Map.ofList |> Ok
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"Mux connected to two MergeWires. Width not inferrable", stateBus8,
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[
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ConnectionId "conn0", None
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ConnectionId "conn1", None
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] |> Map.ofList |> Ok
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"A 4 bit input connected to a four bit output", stateBus13,
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[
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ConnectionId "conn", Some 4
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] |> Map.ofList |> Ok
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"A 2 bit input split into 2 single bit outputs", stateBus16,
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[
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ConnectionId "conn0", Some 2
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ConnectionId "conn1", Some 1
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ConnectionId "conn2", Some 1
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] |> Map.ofList |> Ok
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"3 bit input merged with 4 bit input, then split in the same way", stateBus17,
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[
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ConnectionId "678ffa07-0ed7-7b6f-ba9b-b14839c08a71", Some 7
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ConnectionId "7438de0c-bbaf-c1f6-0307-42ece66c6c00", Some 4
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ConnectionId "82cc4ce9-7b15-40ac-0226-98a7f8e2fb9a", Some 4
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ConnectionId "9df32195-00b4-9795-3dc1-78fb70d453f2", Some 3
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ConnectionId "cd13c70f-6037-0cf4-1295-5795e92d745c", Some 3
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] |> Map.ofList |> Ok
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"Partially connected Mux2", stateBus18,
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[
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ConnectionId "conn-sel", Some 1
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ConnectionId "conn-top-input", Some 2
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ConnectionId "conn-to-output", Some 2
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] |> Map.ofList |> Ok
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"Partially connected Demux2", stateBus20,
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[
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ConnectionId "conn-to-input", Some 2
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ConnectionId "conn-to-output", Some 2
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] |> Map.ofList |> Ok
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]
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let private testCasesWidthInfererError : WidhtInfererTestCase list = [
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"Two inputs connected to the same output", state5,
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Error {
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Msg = "A wire must have precisely one driving component. If you want to merge two wires together, use a MergeWires component."
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ConnectionsAffected = ["conn1"; "conn0"] |> List.map ConnectionId
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}
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"Two inputs; one And; one output; with extra connection input to output", state7,
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Error {
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Msg = "A wire must have precisely one driving component. If you want to merge two wires together, use a MergeWires component."
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ConnectionsAffected = ["conn3"; "conn2"] |> List.map ConnectionId
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}
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"And connected to a SplitWire 1", stateBus9,
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Error {
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Msg = "Wrong wire width. Target port expects a signal with at least 2 bits, but source port produces a 1 bit(s) signal."
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ConnectionsAffected = ["conn0"] |> List.map ConnectionId
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}
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"A 4 bit input connected to a 3 bit output", stateBus14,
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Error {
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Msg = "Wrong wire width. Target port expects a 3 bit(s) signal, but source port produces a 4 bit(s) signal."
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ConnectionsAffected = ["conn"] |> List.map ConnectionId
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}
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"A 3 bit input connected to a 4 bit output", stateBus15,
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Error {
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Msg = "Wrong wire width. Target port expects a 4 bit(s) signal, but source port produces a 3 bit(s) signal."
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ConnectionsAffected = ["conn"] |> List.map ConnectionId
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}
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"Fully connected Mux, but two inputs have different widths", stateBus19,
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Error {
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Msg = "Wrong wire width. The two inputs to a multiplexer are expected to have the same width, but top input has 2 bits and bottom input has 1 bits."
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ConnectionsAffected = ["conn-top-input"; "conn-bottom-input"] |> List.map ConnectionId
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}
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]
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let testCasesWidthInferer : WidhtInfererTestCase list =
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testCasesWidthInfererSimple @
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testCasesWidthInfererBuses @
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testCasesWidthInfererError
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