From 8e47dd469661341d25810d4720fac3da4b7f0cef Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Fri, 16 Sep 2022 11:39:12 +0100
Subject: [PATCH] Add brief project description

---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 63b0a65..463da3b 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,5 @@
 # ELEC60011: Digital System Design - Coursework
 
 - [Coursework Specification](./DSD_coursework_DE1-SoC.pdf)
+
+The goal for this project was to create a custom instruction and hardware to support the custom instruction, with the effect of hardware accelerating a specific computation, and returning the result to the NIOs II soft-core processor. The custom logic was designed in SystemVerilog and instantiated on the FPGA fabric alongside the NIOS II core and other hardware such as timers and interruprt handlers. The project was completed in Quartus Prime 21.1 Lite and tested with the Altera DE1 board.