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61 lines
1.6 KiB
Plaintext
61 lines
1.6 KiB
Plaintext
MIPS 32 bits
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== Bits, Bytes, Hex ==
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-- 8 bits = 1 byte = 2 hex
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-- 32 bits = 4 bytes = 8 hex
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-- e.g. 00000000 00000000 00000000 00000000 -> 0x00000000
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== CPU ==
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inputs:
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-- manual MIPS assembly code -> instructions in binaries
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-- C code -> compiled c program under mips -> disassemble binaries -> assembly code -> instruction in binaries
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-- these binary instructions goes into instruction memory
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outputs:
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-- output of the instructions
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errors:
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-- ?????? how do we detect errors ??????
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== Submodules ==
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-- ALU
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-- Register File
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-- Data Memory
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-- Instruction Register
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-- PC
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-- Control Unit
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== Testbench ==
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-- ????? not so sure yet ?????
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== Endianess ==
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-- big endian: bytes are numbered starting with byte 0 at MSB
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-- use -EB flag to ensure big endian
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== Instruction Access ==
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-- PC (program counter): 32 bit register
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-- PC is initialised to 0xBFC00000
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-- PC changed as instructions are executed
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-- IR = Mem[PC] -> instruction is fetched from data memory using data at the address given by program counter
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Address bus: CPU -> Memory
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Data bus: CPU <=> Memory
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== Register File ==
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-- 32 general-purpose registers
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== Program Counter ==
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-- PC is just a 32 bit register in which the value (address of instruction) get updated by other blocks
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-- Controlled by PCSrc (for branching or regular increment by 4 bytes)
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== Questions ==
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Pseudo-instructions -> how to deal with them -> convert to actual instructions?
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Do we implement big-endian mips?
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What verilator could be useful for
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How would a testbench in c++ be helpful?
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Don't understand that part where we need to implement cache
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== Todo ==
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Testbench in c++
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Cache
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CPU stall cycle
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