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75 lines
2 KiB
Verilog
75 lines
2 KiB
Verilog
module mips_cpu_harvard_tb;
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parameter RAM_INIT_FILE = "inputs/addu.txt";
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parameter TIMEOUT_CYCLES = 100;
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logic clk, clk_enable, reset, active, data_read, data_write;
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logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
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mips_cpu_memory #(RAM_INIT_FILE) ramInst(
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.clk(clk),
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.data_address(data_address),
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.data_write(data_write),
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.data_read(data_read),
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.data_writedata(data_writedata),
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.data_readdata(data_readdata),
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.instr_address(instr_address),
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.instr_readdata(instr_readdata)
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);
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mips_cpu_harvard cpuInst(
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.clk(clk),
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.reset(reset),
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.active(active),
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.register_v0(register_v0),
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.clk_enable(clk_enable),
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.instr_address(instr_address),
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.instr_readdata(instr_readdata),
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.data_address(data_address),
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.data_write(data_write),
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.data_read(data_read),
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.data_writedata(data_writedata),
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.data_readdata(data_readdata)
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);
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// Generate clock
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initial begin
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clk=0;
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repeat (TIMEOUT_CYCLES) begin
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#10;
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clk = !clk;
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#10;
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clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
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end
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initial begin
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$display("Initial Reset 0");
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reset <= 0;
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$display("Initial Reset 1");
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@(posedge clk);
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reset <= 1;
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$display("Initial Reset 0: Start Program");
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@(posedge clk);
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reset <= 0;
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@(posedge clk);
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assert(active==1);
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else $display("TB: CPU did not set active=1 after reset.");
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while (active) begin
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@(posedge clk);
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$display("Register v0: %d", register_v0);
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end
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$display("TB: finished; active=0");
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$display("Output: %d", register_v0);
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$finish;
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end
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endmodule |