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https://github.com/supleed2/ELEC50010-IAC-CW.git
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225 lines
8.4 KiB
Verilog
225 lines
8.4 KiB
Verilog
module mips_cpu_bus(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic[31:0] register_v0,
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/* Avalon memory mapped bus controller (master) */
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output logic[31:0] address,
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output logic write,
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output logic read,
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input logic waitrequest,
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output logic[31:0] writedata,
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output logic[3:0] byteenable,
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input logic[31:0] readdata
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);
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logic[1:0] state; // current state of cpu within cycle
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logic[1:0] n_state; // state to be set at next clk edge
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logic[31:0] instr_reg; // instruction register / single-word cache for current instruction
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logic clk_internal; // modulated clock to be passed to harvard cpu
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logic[31:0] harvard_instr_address; // instr addr from pc
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logic harvard_read; // harvard cpu read flag
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logic harvard_write; // harvard cpu write flag
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logic[31:0] harvard_data_address; // data addr from ALU
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logic[31:0] harvard_readdata; // <= data read from Avalon MM Device
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logic[31:0] harvard_writedata; // data to be written to Avalon MM Device
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logic[3:0] write_byteenable; // byteenable calculator for partial write
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logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
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logic partial_write; // flag to control datapath when doing a partial write
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logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte)
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logic[31:0] write_data_address; // modified data address for partial writes
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initial begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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clk_state = 0;
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end
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always_ff @(posedge clk) begin // CLK Rising Edge
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if (!waitrequest && !clk_state) begin
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case (n_state)
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2'b00: begin // fetch
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clk_internal <= 1'b1;
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state <= 2'b00;
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end
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2'b01: begin // execute
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state <= 2'b01;
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instr_reg <= readdata;
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end
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2'b10: begin // read
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state <= 2'b10;
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end
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2'b11: begin // write
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state <= 2'b11;
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end
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endcase // state
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end
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clk_state <= 1'b1;
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end
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always_ff @(negedge clk) begin // CLK Falling Edge
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if (!waitrequest && clk_state) begin
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case (state)
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2'b00: // nothing happens on fetch negedge
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2'b01: begin // execute negedge
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if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback
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clk_internal <= 1'b0;
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end // otherwise do nothing
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end
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2'b10: begin
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clk_internal <= 1'b0;
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end
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2'b11: begin
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clk_internal <= 1'b0;
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end
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endcase
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end
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clk_state <= 1'b0;
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end
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always_comb begin
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case (instr_reg[31:26])
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6'b101000: begin // Store Byte
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partial_write = 1'b1;
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case (harvard_data_address[1:0])
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2'b00: begin
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partial_writedata = {{24{1'b0}}, harvard_writedata[7:0]};
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write_byteenable = 4'b0001;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b01: begin
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partial_writedata = {{16{1'b0}}, harvard_writedata[7:0], {8{1'b0}}};
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write_byteenable = 4'b0010;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b10: begin
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partial_writedata = {{8{1'b0}}, harvard_writedata[7:0], {16{1'b0}}};
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write_byteenable = 4'b0100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b11: begin
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partial_writedata = {harvard_writedata[7:0], {24{1'b0}}};
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write_byteenable = 4'b1000;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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endcase
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end
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6'b101001: begin // Store Halfword
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partial_write = 1'b1;
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case (harvard_data_address[1:0])
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2'b00: begin
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partial_writedata = {{16{1'b0}}, harvard_writedata[15:0]};
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write_byteenable = 4'b0011;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b01: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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2'b10: begin
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partial_writedata = {harvard_writedata[15:0], {16{1'b0}}};
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write_byteenable = 4'b1100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b11: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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endcase
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end
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default: begin // Store Word OR All other instructions (These flags are ignored outside the write state)
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partial_write = 1'b0;
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partial_writedata = 32'h00000000;
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write_byteenable = 4'b1111;
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write_data_address = harvard_data_address;
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end
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endcase
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end
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always_comb begin
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if (reset) begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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end else begin
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case (state)
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2'b00: begin // connecting wires when in fetch state
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address = harvard_instr_address;
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read = 1'b1;
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write = 1'b0;
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byteenable = 4'b1111;
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harvard_readdata = 32'h00000000;
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writedata = 32'h00000000;
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n_state = 2'b01;
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end
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2'b01: begin // connecting wires when in execute state
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address = 32'h00000000;
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read = 1'b0;
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write = 1'b0;
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byteenable = 4'b0000;
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harvard_readdata = 32'h00000000;
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writedata = 32'h00000000;
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if (harvard_read) begin
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n_state = 2'b10; // next state is read
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end else if (harvard_write) begin
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n_state = 2'b11; // next state is write
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end else begin
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n_state = 2'b00; // next state is fetch
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end
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end
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2'b10: begin // connecting wires when in read state
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address = harvard_data_address;
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read = 1'b1;
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write = 1'b0;
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byteenable = 4'b1111;
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harvard_readdata = readdata;
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writedata = 32'h00000000;
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n_state = 2'b00;
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end
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2'b11: begin // connecting wires when in write state
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address = write_data_address;
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read = 1'b0;
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write = 1'b1;
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byteenable = write_byteenable;
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harvard_readdata = 32'h00000000;
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writedata = partial_write ? partial_writedata : harvard_writedata;
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n_state = 2'b00;
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end
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endcase // state
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end
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end
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mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
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.clk(clk_internal), // modulated clock input to allow waiting for valid data from memory, input
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.reset(reset), // CPU reset, input
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.active(active), // Is CPU active, output
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.register_v0(register_v0), // $2 / $v0 debug bus, output
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.clk_enable(1'b0), // unused clock enable, input
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.instr_address(harvard_instr_address), // instr addr from pc, output
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.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
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.data_address(harvard_data_address), // harvard data memory address, output
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.data_write(harvard_write), // harvard write flag, output
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.data_read(harvard_read), // harvard read flag, output
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.data_writedata(harvard_writedata), // data output from regfile readport2, output
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.data_readdata(harvard_readdata) // data in from read instruction, input
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);
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endmodule
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