mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-09-20 03:56:18 +00:00
903 lines
9.5 KiB
Plaintext
903 lines
9.5 KiB
Plaintext
== Instruction ==
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Assembly code
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Hex code
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Reference Output
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================
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==ADDIU Add immediate unsigned (no overflow)==
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ORI $4,$0,0xA
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JR $0
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ADDIU $2,$4,20
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3404000a
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00000008
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24820014
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register_v0 = 30
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== ADDU Add unsigned (no overflow) ==
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ORI $4,$0,3
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ORI $5,$0,5
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JR $0
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ADDU $2,$4,$5
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34040003
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34050005
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00000008
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00851021
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register_v0 = 8
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-Test not overflowing property
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lui $4,$0,0x1000
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lui $5,$0,0xF000
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JR $0
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ADDU $2,$4,$5
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3C041000
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3C05F000
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00000008
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00851021
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register_v0 = 0
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==AND Bitwise and==
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LUI $5,0xCCCC
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ORI $5,$5,0xCCCC
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LUI $4,0xAAAA
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ORI $4,$4,0xAAAA
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JR $0
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AND $2,$4,$5
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3c05cccc
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34A5cccc
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3c04aaaa
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3484aaaa
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00000008
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00851024
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register_v0 = 0x88888888 / 2290649224
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==ANDI Bitwise and immediate==
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LUI $4,0xAAAA
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ORI $4,$0,0xAAAA
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JR $0
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ANDI $2,$4,0xCCCC
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3c04aaaa
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3404aaaa
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00000008
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3082cccc
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register_v0 = 0x00008888 / 34952
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==BEQ Branch on equal==
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ORI $4,$0,5
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ORI $5,$0,5
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BEQ $4,$5,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040005
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34050005
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10850003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BGEZ Branch on greater than or equal to zero==
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ORI $4,$0,3
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BGEZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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04810003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BGEZAL Branch on non-negative (>=0) and link==
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ORI $4,$0,3
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BGEZAL $4,4
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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34040003
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04910004
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00000000
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24420001
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00000008
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00000000
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34020001
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03E00008
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register_v0 = 2
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-Testing whether it would link if branch fails
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lui $4,0xFFFF
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BGEZAL $4,4
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JR $31
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ADDIU $2,$2,1
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JR $0
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3C04FFFF
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04910004
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03E00008
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24420001
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00000008
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register_v0 = 2
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==BGTZ Branch on greater than zero==
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ORI $4,$0,3
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BGTZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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1C800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLEZ Branch on less than or equal to zero==
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LUI $4,0xFFFF
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BLEZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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3C05FFFF
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18800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLTZ Branch on less than zero==
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LUI $4,0xFFFF
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BLTZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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3C04FFFF
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04800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLTZAL Branch on less than zero and link==
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LUI $4,0xFFFF
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BLTZAL $4,4
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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3C05FFFF
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04900004
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00000000
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24420001
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00000008
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00000000
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34020001
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03E00008
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register_v0 = 2
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==BNE Branch on not equal==
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ORI $4,$0,3
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ORI $5,$0,5
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BNE $4,$5,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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34040005
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14850003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==DIV Divide== //May need other testcases for -ve/+ve, -ve/-ve
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ORI $4,$0,3
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ORI $5,$0,9
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DIV $5,$4
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MFHI $4
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MFLO $5
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ADDU $2,$4,$5
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JR $0
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34040003
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34050009
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00A4001A
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00002010
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00002812
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00851021
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00000008
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register_v0 = 3
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==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
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LUI $4,0x8000
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ORI $5,$0,2
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DIVU $4,$5
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MFHI $4
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MFLO $5
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ADDU $2,$4,$5
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JR $0
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3C048000
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34050002
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0085001B
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00002010
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00002812
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00851021
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00000008
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register_v0 = 0x40000000 / 1073741824
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==J Jump==
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J 4
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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08000004
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==JALR Jump and link register==
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LUI $5,0xBFC0
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ORI $5,$5,0x001C
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JALR $4,$5
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $4
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3C05BCF0
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34A5001C
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00A02009
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00000000
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24420001
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00000008
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00000000
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34020001
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00800008
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register_v0 = 2
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==JAL Jump and link==
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JAL 5
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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0C000005
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00000000
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24420001
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00000008
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00000000
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34020001
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03E00008
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register_v0 = 2
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==JR Jump register==
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LUI $5,0xBFC0
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ORI $5,$5,0x0014
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JR $5
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NOP
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JR $0
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NOP
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ORI $2,$0,0xA
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JR $0
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3C05BFC0
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34A50014
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00A00008
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00000000
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00000008
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3402000A
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00000008
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register_v0 = 10
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-Branch Delay slot test
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JR $0
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ORI $2,$0,5
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00000008
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34020005
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register_v0 = 5
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-This broke testbench once due to log.txt weirdness
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LUI $5,0xBFC0
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ORI $5,$5,0x0008
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JR $5
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JR $0
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3C05BFC0
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34A50008
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00A00008
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00000008
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register_v0 = 0
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==LB Load byte==
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ORI $4,$0,0x1001
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JR $0
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LB $2,5($4)
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-Instruction Hex
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34041001
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00000008
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80820005
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-Memory Hex
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00000000
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008A0000
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00000000
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00000000
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register_v0 = 0xFFFFFF8A / 4294967178
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==LBU Load byte unsigned==
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ORI $4,$0,0x1002
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JR $0
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LBU $2,4($4)
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-Instruction Hex
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34041002
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00000008
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90820004
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-Memory Hex
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00000000
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008A0000
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00000000
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00000000
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register_v0 = 0x0000008A / 138
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==LH Load half-word==
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ORI $4,$0,0x1000
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JR $0
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LH $2,4($4)
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-Instruction Hex
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34041003
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00000008
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84820004
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-Memory Hex
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00000000
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00008123
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00000000
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00000000
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register_v0 = 0xFFFF8123 / 4294934819
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==LHU Load half-word unsigned==
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ORI $4,$0,0x1000
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JR $0
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LHU $2,4($4)
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-Instruction Hex
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34041000
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00000008
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94820004
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-Memory Hex
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00000000
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00008123
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00000000
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00000000
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register_v0 = 0x00008123 / 33059
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==LUI Load upper immediate==
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LUI $2,0x1234
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ORI $2,$2,0x5678
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JR $0
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3C021234
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34425678
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00000008
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register_v0 = 0x12345678 / 305419896
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==LW Load word==
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ORI $4,$0,0x1002
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JR $0
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LW $2, 2($4)
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-Instruction Hex
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34041002
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00000008
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8C820002
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-Memory Hex
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00000000
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12345678
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00000000
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00000000
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register_v0 = 0x12345678 / 305419896
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==LWL Load word left==
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ORI $4,$0,0x1001
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ORI $2,$0,0x5678
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JR $0
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LWL $2,3($4)
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-Instruction Hex
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34041001
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34025678
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00000008
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88820003
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-Memory Hex
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00000000
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AAAA1234
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00000000
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00000000
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register_v0 = 0x12345678 / 305419896
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==LWR Load word right==
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LUI $2,0x1234
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ORI $4,$0,0x1002
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JR $0
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LWR $2,3($4)
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-Instruction Hex
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3C021234
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34041002
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00000008
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98820003
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-Memory Hex
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00000000
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5678AAAA
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00000000
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00000000
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register_v0 = 0x12345678 / 305419896
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==MTHI Move to HI==
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ori $4, $0, 5
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mthi $4
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mfhi $2
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jr $0
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34040005
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00800011
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00001010
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00000008
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register_v0 = 5
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==MTLO Move to LO==
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ori $4, $0, 5
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mtlo $4
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mflo $2
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jr $0
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34040005
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00800013
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00001012
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00000008
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register_v0 = 5
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==MULT Multiply==
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ori $4, $0, 4
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ori $5, $0, 3
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mult $4, $5
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mflo $2
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jr $0
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34040004
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34050003
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00850018
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00001012
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00000008
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register_v0 = 12
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==MULTU Multiply unsigned==
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ori $4, $0, 4
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ori $5, $0, 3
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multu $4, $5
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mflo $2
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jr $0
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34040004
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34050003
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00850019
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00001012
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00000008
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register_v0 = 12
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==OR Bitwise or==
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ori $4, $0, 5
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ori $5, $0, 3
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jr $0
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or $2, $4, $5
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34040005
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34050003
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00000008
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00851025
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register_v0 = 7
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==ORI Bitwise or immediate==
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ori $4, $0, 0xFFFF
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ori $5, $0, 0x1234
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jr $0
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or $2, $4, $5
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3404FFFF
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34051234
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00851025
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00000008
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register_v0 = 65535
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==SB Store byte==
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lui $4, 0x1234
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ori $4, $0, 0x5678
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lui $5, 0xBFC0
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ori $5, $0, 0x001C
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sb $4, 0($5)
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lb $2, 0($5)
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jr $0
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3C041234
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34045678
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3C05BFC0
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3405001C
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A0A40000
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80A20000
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00000008
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register_v0 = 0x00000078
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==SH Store half-word==
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lui $4, 0x1234
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ori $4, $0, 0x5678
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lui $5, 0xBFC0
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ori $5, $0, 0x001C
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sh $4, 0($5)
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lh $2, 0($5)
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jr $0
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3C041234
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34045678
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3C05BFC0
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3405001C
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A4A40000
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84A40000
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00000008
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register_v0 = 0x00005678
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==SLL Shift left logical==
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ori $4,$0,3
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jr $0
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sll $2,$4,2
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34040003
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00000008
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00041080
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register_v0 = 12
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==SLLV Shift left logical variable==
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ori $4,$0,2
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ori $5,$0,3
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jr $0
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sllv $2,$5,$4
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34040002
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34050003
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00000008
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00851004
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register_v0 = 12
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==SLT Set on less than (signed)==
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ORI $4 $zero 0xFFFF
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ORI $5 $zero 0x000B
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jr $0
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SLT $2 $4 $5
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3404FFFF
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3405000B
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00000008
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0085102A
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register_v0 = 0
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==SLTI Set on less than immediate (signed)==
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ori $4, $0, 10
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jr $0
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slti $2, $4, 9
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3404000a
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00000008
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28820009
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register_v0 = 0
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==SLTIU Set on less than immediate unsigned==
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ori $4, $0, 10
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jr $0
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sltiu $2, $4, 9
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3404000a
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00000008
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2c820009
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register_v0 = 0
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==SLTU Set on less than unsigned==
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ori $4, $0, 10
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ori $5, $0, 9
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jr $0
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sltu $2, $4, $5
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3404000a
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34050009
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00000008
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0085102b
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register_v0 = 0
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==SRA Shift right arithmetic==
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lui $5 $0,0xF000
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jr $0
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srav $2,$5,2
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3C05F000
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00000008
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00051083
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register_v0 = 0xFC000000 / 4227858432
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==SRAV Shift right arithmetic variable==
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ori $4,$0,2
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lui $5, 0xF000
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jr $0
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srav $2,$5,$4
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34040002
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3C05F000
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00000008
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00851007
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register_v0 = 0xFC000000 / 4227858432
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==SRL Shift right logical==
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ori $4,$0,16
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jr $0
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srl $2,$4,2
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34040010
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00000008
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00041082
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register_v0 = 4
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==SRLV Shift right logical variable==
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ori $4,$0,2
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ori $5,$0,16
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jr $0
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srlv $2,$5,$4
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34040002
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34050010
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00000008
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00851006
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register_v0 = 4
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==SUBU Subtract unsigned==
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ori $4,$0,5
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ori $5,$0,3
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jr $0
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subu $2,$4,$5
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34040005
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34050003
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00000008
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00851023
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register_v0 = 2
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==SW Store word==
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ori $4, $0, 0xFFFF
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ori $5, $0, 0x1008
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sw $4, 4($5)
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lw $2, 4($5)
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jr $0
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3404FFFF
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34051008
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ACA40004
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|
8CA20004
|
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00000008
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|
|
|
register_v0 = 0x0000FFFF / 65535
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-Negative Offset
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ori $4, $0, 0xFFFF
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ori $5, $0, 0x1008
|
|
sw $4, -4($5)
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|
lw $2, -4($5)
|
|
jr $0
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|
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|
3404FFFF
|
|
34051008
|
|
ACA4FFFC
|
|
8CA2FFFC
|
|
00000008
|
|
|
|
register_v0 = 0x0000FFFF / 65535
|
|
|
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==XOR Bitwise exclusive or==
|
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|
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ori $4, $0, 5
|
|
ori $5, $0, 2
|
|
jr $0
|
|
xor $2, $4, $5
|
|
|
|
34040005
|
|
34050002
|
|
00000008
|
|
00851026
|
|
|
|
register_v0 = 7
|
|
|
|
==XORI Bitwise exclusive or immediate==
|
|
|
|
ori $4,$0,5
|
|
jr $0
|
|
xori $2,$4,0x000F
|
|
|
|
34040005
|
|
00000008
|
|
3882000F
|
|
|
|
register_v0 = 10
|