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61 lines
1.2 KiB
Verilog
61 lines
1.2 KiB
Verilog
module CPU_MU0_delay1_tb;
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timeunit 1ns / 10ps;
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parameter RAM_INIT_FILE = "test/01-binary/countdown.hex.txt";
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parameter TIMEOUT_CYCLES = 10000;
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logic clk;
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logic rst;
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logic running;
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logic[11:0] address;
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logic write;
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logic read;
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logic[15:0] writedata;
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logic[15:0] readdata;
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RAM_16x4096_delay1 #(RAM_INIT_FILE) ramInst(clk, address, write, read, writedata, readdata);
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CPU_MU0_delay1 cpuInst(clk, rst, running, address, write, read, writedata, readdata);
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// Generate clock
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initial begin
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clk=0;
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repeat (TIMEOUT_CYCLES) begin
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#10;
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clk = !clk;
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#10;
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clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
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end
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initial begin
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rst <= 0;
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@(posedge clk);
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rst <= 1;
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@(posedge clk);
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rst <= 0;
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@(posedge clk);
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assert(running==1)
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else $display("TB : CPU did not set running=1 after reset.");
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while (running) begin
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@(posedge clk);
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end
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$display("TB : finished; running=0");
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$finish;
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end
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endmodule |