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52 lines
1.8 KiB
Verilog
52 lines
1.8 KiB
Verilog
/*
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Data Memory for Harvard Interface
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- RAM Size: 32 x 2^32 = 32 x 4294967296
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- Zero-cycle / combinatorial reads
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- Instruction in binaries or hex -> RAM_INIT_FILE
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Needs checking with:
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-- clk_enable input being used instead of clk
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-- whether there is a more efficient way of initialising memory to zero (line 32)
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-- how to implement given that you cannot read and write in the same cycle (line 48)
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-- special memory locations: 0x00000000 (CPU halt), 0xBFC00000 (start execution after reset)
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-> Should PC be 0xBFC00000 at the start and 0x00000000 at the end?
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-> And should instructions start from 0xBFC00000?
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-> Put halt instruction at 0x00000000 by default? - What is the halt instruction?
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*/
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module mips_cpu_data_memory(
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input logic clk_enable,
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input logic[31:0] data_address,
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input logic data_write,
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input logic data_read,
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input logic[31:0] data_writedata,
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output logic[31:0] data_readdata
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);
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parameter RAM_INIT_FILE = "";
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reg [31:0] memory [4294967295:0];
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initial begin
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integer i;
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/* Initialise to zero by default */
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for (i=0; i<4294967296; i++) begin
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memory[i]=0;
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end
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/* Load contents from file if specified */
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if (RAM_INIT_FILE != "") begin
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory);
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end
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end
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/* Combinatorial read path. */
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assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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/* Synchronous write path */
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always_ff @(posedge clk_enable) begin
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//$display("RAM : INFO : data_read=%h, data_addr = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin
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memory[data_address] <= data_writedata;
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end
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end
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endmodule |