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17 lines
419 B
Verilog
17 lines
419 B
Verilog
module mips_cpu_bus(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic[31:0] register_v0,
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/* Avalon memory mapped bus controller (master) */
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output logic[31:0] address,
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output logic write,
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output logic read,
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input logic waitrequest,
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output logic[31:0] writedata,
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output logic[3:0] byteenable,
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input logic[31:0] readdata
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);
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