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66 lines
2.3 KiB
Verilog
66 lines
2.3 KiB
Verilog
module regfile(
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input logic clk, //clock input for triggering write port
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input logic[4:0] readreg1, //read port 1 selector
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input logic[4:0] readreg2, //read port 2 selector
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input logic[4:0] writereg, //write port selector
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input logic[31:0] writedata, //write port input data
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input logic regwrite, //enable line for write port
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input[5:0] opcode, //opcode input for controlling partial load weirdness
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output logic[31:0] readdata1, //read port 1 output
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output logic[31:0] readdata2, //read port 2 output
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output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
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);
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reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
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initial begin
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integer i; //Initialise to zero by default
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for (i = 0; i < 31; i++) begin
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memory[i] = 0;
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end
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end
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assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
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always_comb begin
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readdata1 = memory[readreg1]; //combinatorially output register value based on read port 1 selector
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readdata2 = memory[readreg2]; //combinatorially output register value based on read port 2 selector
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end
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always_ff @(negedge clk) begin
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if (regwrite) begin
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case (opcode)
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6'b100000: begin //lb, load byte
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memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
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end
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6'b100100: begin //lbu, load byte unsigned
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memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
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end
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6'b100001: begin //lh, load half-word
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memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
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end
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6'b100101: begin //lhu, load half-word unsigned
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memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
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end
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6'b100010: begin //lwl, load word left
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case (readdata1[1:0])
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2'b00: memory[writereg][31:24] <= writedata[7:0];
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2'b01: memory[writereg][31:16] <= writedata[15:0];
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2'b10: memory[writereg][31:8] <= writedata[23:0];
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2'b11: memory[writereg][31:0] <= writedata[31:0];
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endcase // readdata1[1:0]
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end
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6'b100110: begin //lwr, load word right
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case (readdata1[1:0])
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2'b00: memory[writereg][31:0] <= writedata[31:0];
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2'b01: memory[writereg][23:0] <= writedata[31:8];
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2'b10: memory[writereg][15:0] <= writedata[31:16];
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2'b11: memory[writereg][7:0] <= writedata[31:24];
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endcase // readdata1[1:0]
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end
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default: memory[writereg] <= writedata; //most instructions
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endcase // opcode
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end
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end
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endmodule : regfile |