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54 lines
1.1 KiB
Verilog
54 lines
1.1 KiB
Verilog
module mips_cpu_pc(
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input logic clk,
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input logic rst,
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input logic[1:0] pc_ctrl,
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input logic[31:0] instr,
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input logic[31:0] reg_readdata,
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output logic[31:0] pc_out,
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output logic active
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);
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reg [31:0] pc_next, pc_lit_next;
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initial begin
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pc_out = 32'hBFC00000;
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pc_next = pc_out + 32'd4;
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end
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assign pc_lit_next = pc_out + 32'd4;
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always_ff @(posedge clk) begin
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if (rst) begin
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active <= 1;
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pc_out <= 32'hBFC00000;
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end else begin
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if(pc_out == 32'd0) begin
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active <= 0;
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end
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pc_out <= pc_next;
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end
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end
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always_comb begin
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case(pc_ctrl)
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2'd1: begin // Branch
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pc_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00};
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end
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2'd2: begin // Jump
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pc_next = {pc_lit_next[31:28], instr[25:0], 2'b00};
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$display("JUMPING");
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$display("pc_lit_next: %h", pc_lit_next[31:28]);
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$display("instr: %b", instr[25:0]);
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$display("%h",pc_next);
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end
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2'd3: begin // Jump using Register
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pc_next = reg_readdata;
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end
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default: begin
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pc_next = pc_out + 32'd4;
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end
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endcase
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end
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endmodule // pc
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