mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-11-10 01:35:49 +00:00
274 lines
3 KiB
Plaintext
274 lines
3 KiB
Plaintext
===== ADDIU ==========
|
|
int main(void) {
|
|
int a = -2147483648 + -32768 ;
|
|
}
|
|
|
|
ORI $4,$0,-2147483648
|
|
ADDIU $2,$4,-32768
|
|
JR $0
|
|
|
|
//used to check for overflow 32768 is 2^15 which should
|
|
be sign extended. 21... is 2^31
|
|
|
|
|
|
register_v0 =
|
|
|
|
==========XORI Bitwise exclusive or immediate=============
|
|
|
|
int main(void) {
|
|
int a = 5 ^ 2;
|
|
}
|
|
|
|
ori $4,$0,5
|
|
xori $2,$4,2
|
|
jr $0
|
|
|
|
register 0 = 7
|
|
|
|
34040005
|
|
38820002
|
|
00000008
|
|
|
|
convert to little endian
|
|
|
|
////////
|
|
|
|
====XOR Bitwise exclusive or==========
|
|
|
|
int main(void) {
|
|
int a = 5 ^ 2;
|
|
}
|
|
|
|
ori $4, $0, 5
|
|
ori $5, $0, 2
|
|
xor $2, $4, $5
|
|
jr $0
|
|
|
|
register 0 = 7
|
|
|
|
34040005
|
|
34050002
|
|
00851026
|
|
00000008
|
|
|
|
convert to little endian
|
|
|
|
////////
|
|
|
|
========SW Store word==============
|
|
|
|
int main(void) {
|
|
|
|
|
|
ori $4, $0, 5
|
|
ori $5, $0, 1
|
|
sw $4, 1($5)
|
|
jr $0
|
|
|
|
register 0 = 5
|
|
|
|
34040005
|
|
34050001
|
|
aca40001
|
|
00000008
|
|
|
|
|
|
=========== SUBU Subtract unsigned ===========
|
|
|
|
int main(void) {
|
|
int a = 5-3;
|
|
}
|
|
|
|
ori $4,$0,5
|
|
ori $5,$0,3
|
|
subu $2,$4,$5
|
|
jr $0
|
|
|
|
|
|
register_v0 = 2
|
|
|
|
|
|
34040005
|
|
34050003
|
|
00851023
|
|
00000008
|
|
|
|
|
|
========= SRLV Shift right logical variable ======
|
|
|
|
|
|
int main(void) {
|
|
int a = 2;
|
|
int b = 16>>a;
|
|
}
|
|
|
|
ori $4,$0,2
|
|
ori $5,$0,16
|
|
srlv $2,$5,$4
|
|
jr $0
|
|
|
|
register 0 = 3
|
|
|
|
34040002
|
|
34050010
|
|
//////
|
|
//////
|
|
|
|
=============== SRL Shift right logical ==============
|
|
|
|
|
|
int main(void) {
|
|
int a = -2147483647>>2; #logical shift - should feed in 0s
|
|
}
|
|
|
|
ori $4,$0,-2147483647
|
|
srl $2,$4,$2
|
|
jr $0
|
|
|
|
register 0 = 536870912 (2^29)
|
|
|
|
34040001
|
|
00041002
|
|
00000008
|
|
|
|
========== SRAV Shift right arithmetic variable =======
|
|
|
|
int main(void) {
|
|
int a = 2;
|
|
int b = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
|
|
}
|
|
|
|
ori $4, $0, 2
|
|
ori $5,$0,-2147483647
|
|
srav $2,$5,$4
|
|
jr $0
|
|
|
|
register 0 = -536870912 (first 3 bits high - rest low)
|
|
|
|
34040002
|
|
34050001
|
|
////////
|
|
///////
|
|
|
|
====== SRA Shift right arithmetic ==========
|
|
|
|
int main(void) {
|
|
int a = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
|
|
}
|
|
|
|
|
|
ori $4,$0,-2147483647
|
|
sra $2,$4,$2
|
|
jr $0
|
|
|
|
register 0 = -536870912 (first 3 bits high - rest low)
|
|
|
|
34040001
|
|
00041003
|
|
00000008
|
|
|
|
======= SLTU Set on less than unsigned =====
|
|
|
|
int main() {
|
|
int a = 10;
|
|
int b = 9;
|
|
|
|
max = a < b ? 1 : 0;
|
|
|
|
return max;
|
|
}
|
|
|
|
|
|
ori $4, $0, 10
|
|
ori $5, $0, 9
|
|
sltu $2, $4, $5
|
|
jr $0
|
|
|
|
register 0 = 0
|
|
|
|
3404000a
|
|
34050009
|
|
0085102b
|
|
00000008
|
|
|
|
=========== SLTIU Set on less than immediate unsigned ==================
|
|
|
|
int main() {
|
|
int a = 10;
|
|
|
|
max = a < 9 ? 1 : 0;
|
|
|
|
return max;
|
|
}
|
|
|
|
|
|
ori $4, $0, 10
|
|
sltiu $2, $4, 9
|
|
jr $0
|
|
|
|
register 0 = 0
|
|
|
|
3404000a
|
|
2c820009
|
|
00000008
|
|
|
|
======= SLTI Set on less than immediate (signed) ========
|
|
|
|
int main() {
|
|
int a = 10;
|
|
|
|
max = a < 9 ? 1 : 0;
|
|
|
|
return max;
|
|
}
|
|
|
|
|
|
ori $4, $0, 10
|
|
slti $2, $4, 9
|
|
jr $0
|
|
|
|
register 0 = 0
|
|
|
|
3404000a
|
|
28820009
|
|
00000008
|
|
|
|
|
|
|
|
======= SLLV Shift left logical variable ======
|
|
|
|
|
|
int main(void) {
|
|
int a = 2;
|
|
int b = 3<<a;
|
|
}
|
|
|
|
ori $4,$0,2
|
|
ori $5,$0,3
|
|
sllv $2,$5,$4
|
|
jr $0
|
|
|
|
register 0 = 16
|
|
|
|
34040002
|
|
34050003
|
|
//////
|
|
//////
|
|
|
|
|
|
======= SLL Shift left logical ======
|
|
|
|
|
|
int main(void) {
|
|
int a = 3<<2;
|
|
}
|
|
|
|
ori $4,$0,3
|
|
sll $2,$4,2
|
|
jr $0
|
|
|
|
register 0 = 16
|
|
|
|
34040003
|
|
00041080
|
|
00000008 |