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https://github.com/supleed2/ELEC50010-IAC-CW.git
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943745a1e0
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
483 lines
4.8 KiB
Plaintext
483 lines
4.8 KiB
Plaintext
===== ADDIU ==========
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int main(void) {
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int a = -2147483648 + -32768 ;
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}
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ORI $4,$0,-2147483648
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ADDIU $2,$4,-32768
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JR $0
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//used to check for overflow 32768 is 2^15 which should
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be sign extended. 21... is 2^31
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register_v0 =
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==========XORI Bitwise exclusive or immediate=============
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int main(void) {
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int a = 5 ^ 2;
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}
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ori $4,$0,5
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xori $2,$4,2
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jr $0
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register 0 = 7
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34040005
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38820002
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00000008
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convert to little endian
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////////
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====XOR Bitwise exclusive or==========
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int main(void) {
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int a = 5 ^ 2;
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}
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ori $4, $0, 5
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ori $5, $0, 2
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xor $2, $4, $5
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jr $0
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register 0 = 7
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34040005
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34050002
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00851026
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00000008
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convert to little endian
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////////
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========SW Store word==============
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int main(void) {
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ori $4, $0, 5
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ori $5, $0, 1
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sw $4, 1($5)
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jr $0
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register 0 = 5
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34040005
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34050001
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aca40001
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00000008
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=========== SUBU Subtract unsigned ===========
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int main(void) {
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int a = 5-3;
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}
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ori $4,$0,5
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ori $5,$0,3
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subu $2,$4,$5
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jr $0
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register_v0 = 2
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34040005
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34050003
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00851023
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00000008
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========= SRLV Shift right logical variable ======
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int main(void) {
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int a = 2;
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int b = 16>>a;
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}
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ori $4,$0,2
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ori $5,$0,16
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srlv $2,$5,$4
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jr $0
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register 0 = 3
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34040002
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34050010
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//////
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//////
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=============== SRL Shift right logical ==============
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int main(void) {
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int a = -2147483647>>2; #logical shift - should feed in 0s
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}
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ori $4,$0,-2147483647
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srl $2,$4,$2
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jr $0
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register 0 = 536870912 (2^29)
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34040001
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00041002
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00000008
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========== SRAV Shift right arithmetic variable =======
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int main(void) {
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int a = 2;
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int b = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
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}
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ori $4, $0, 4
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ori $5,$0,0xF000
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srav $2,$5,$4
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SRAv $v0 $a1 $a0
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jr $0
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register 0 = -536870912 (first 3 bits high - rest low)
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34040004
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3405F000
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////////
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///////
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====== SRA Shift right arithmetic ==========
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int main(void) {
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int a = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
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}
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ori $4,$0,-2147483647
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sra $2,$4,$2
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jr $0
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register 0 = -536870912 (first 3 bits high - rest low)
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34040001
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00041003
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00000008
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======= SLTU Set on less than unsigned =====
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int main() {
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int a = 10;
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int b = 9;
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max = a < b ? 1 : 0;
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return max;
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}
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ori $4, $0, 10
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ori $5, $0, 9
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sltu $2, $4, $5
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jr $0
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register 0 = 0
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3404000a
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34050009
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0085102b
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00000008
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=========== SLTIU Set on less than immediate unsigned ==================
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int main() {
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int a = 10;
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max = a < 9 ? 1 : 0;
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return max;
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}
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ori $4, $0, 10
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sltiu $2, $4, 9
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jr $0
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register 0 = 0
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3404000a
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2c820009
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00000008
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======= SLTI Set on less than immediate (signed) ========
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int main() {
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int a = 10;
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max = a < 9 ? 1 : 0;
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return max;
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}
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ori $4, $0, 10
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slti $2, $4, 9
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jr $0
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register 0 = 0
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3404000a
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28820009
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00000008
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======= SLLV Shift left logical variable ======
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int main(void) {
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int a = 2;
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int b = 3<<a;
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}
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ori $4,$0,2
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ori $5,$0,3
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sllv $2,$5,$4
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jr $0
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register 0 = 16
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34040002
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34050003
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//////
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//////
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======= SLL Shift left logical ======
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int main(void) {
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int a = 3<<2;
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}
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ori $4,$0,3
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sll $2,$4,2
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jr $0
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register 0 = 16
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34040003
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00041080
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00000008
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======== SB Store byte =======
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ori $4, $0, 1029
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ori $5, $0, 1
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sb $4, 1($5)
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jr $0
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register 0 = 5
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34040405
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34050001
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a0a40001
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00000008
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======== ORI Bitwise or immediate ===
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ori $4,$0,3
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jr $0
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register a0 = 3
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34040003
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00000008
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======== OR Bitwise or ===
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int main(){
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int a =5;
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int b= 3;
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int c = 5 | 3;
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return 0;
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}
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ori $4, $0, 5
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ori $5, $0, 3
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or $2, $4, $5
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jr $0
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34040005
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34050003
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00851025
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00000008
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register 0 = 7
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======= MULT Multiply =====
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ori $4, $0, 4
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ori $5, $0, 3
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mult $4, $5
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jr $0
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$LO = 12
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34040004
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34050003
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00850018
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00000008
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======= MULT Multiply =====
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ori $4, $0, 4
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ori $5, $0, 3
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mult $4, $5
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mflo $2
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jr $0
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register v0 = 12
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34040004
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34050003
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00850018
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00001012
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00000008
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======= MULTU Multiply unsigned =====
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ori $4, $0, 4
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ori $5, $0, 3
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multu $4, $5
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jr $0
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$LO = 12
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34040004
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34050003
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00850019
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00000008
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======= MULTU Multiply unsigned =====
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ori $4, $0, 4
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ori $5, $0, 3
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multu $4, $5
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mflo $2
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jr $0
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$2 = 12
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34040004
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34050003
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00850019
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00001012
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00000008
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======= MFLO Move from lo ======
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ori $4, $0, 4
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ori $5, $0, 3
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multu $4, $5
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mflo $2
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jr $0
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$2 = 12
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34040004
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34050003
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00850019
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00001012
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00000008
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=========== MFHI Move from Hi ==========
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ori $4, $0, 3
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mthi $4
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mfhi $2
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jr $0
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register v0 = 3
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34040003
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00800011
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00001010
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00000008
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======== MTHI Move to HI ====
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ori $4, $0, 5
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mthi $4
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jr $0
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$HI = 5
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34040005
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00800011
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00000008
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======= MTLO Move to LO ===
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ori $4, $0, 5
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mtlo $4
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jr $0
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$HI = 5
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34040005
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00800013
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00000008
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==================== SH Store half-word =======
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/////////
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======== DIV Divide ======
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ori $4, $0, 4
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ori $5, $0, 3
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div $4, $5
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jr $0
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$LO = 1
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$HI = 1
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34040004
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34050003
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0085001A
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00000008
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========= DIVU Divide unsigned =====
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ori $4, $0, 4
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ori $5, $0, 3
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divu $4, $5
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jr $0
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$LO = 1
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$HI = 1
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34040004
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34050003
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0085001B
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00000008 |