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83 lines
2.7 KiB
Verilog
83 lines
2.7 KiB
Verilog
/*
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Memory for Harvard Interface
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- RAM Size: 32 x 2^32 = 32 x 4294967296
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- Instructions in binaries or hex -> RAM_INIT_FILE
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- combinatorial read/fetch of instruction via instr_ port
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- combinatorial read and single cycle write of data via data_ port
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Constraints
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read write
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0 0 -> nothing
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0 1 -> write
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1 0 -> read
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1 1 -> read ????? probs should never occur?
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Instantiation of Memory Module
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- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
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Special Memory Locations
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- Whether a particular address maps to RAM, ROM, or something else is entirely down to the top-level circuit outside your CPU.
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- special memory locations: 0x00000000 (CPU halt), 0xBFC00000 (start execution after reset)
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- PC should be 0xBFC00000 at the start and 0x00000000 at the end
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Needs checking with:
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-- clk or clk_enable?
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-- constraint on not being able to read and write in the same cycle
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-- whether there is a more efficient way of initialising memory to zero (line 32)
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*/
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module mips_cpu_memory(
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input logic clk_enable,
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//Data Memory
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input logic[31:0] data_address,
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input logic data_write,
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input logic data_read,
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input logic[31:0] data_writedata,
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output logic[31:0] data_readdata,
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//Instruction Memory
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input logic[31:0] instr_address,
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output logic[31:0] instr_readdata
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);
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parameter RAM_INIT_FILE = "";
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reg [31:0] memory [4294967295:0]; // 2^32 memory locations of 32 bits size
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initial begin
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integer i;
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//Initialise to zero by default
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for (i=0; i<4294967296; i++) begin
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memory[i]=0;
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end
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory);
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end
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end
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//Combinatorial read path for data and instruction.
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if (clk_enable == 1) begin
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assign data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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assign instr_readdata = memory[instr_address];
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end
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else begin
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assign data_readdata = data_readdata;
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assign instr_readdata = instr_address;
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end
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//Synchronous write path
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always_ff @(posedge clk_enable) begin
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//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
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if (instr_address != data_address) begin //cannot modify the instruction being read
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memory[data_address] <= data_writedata;
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end
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end
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end
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endmodule
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