mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-11-12 18:55:48 +00:00
Aadi Desai
f2f8e05010
PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
25 lines
356 B
Verilog
25 lines
356 B
Verilog
module pc(
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input logic clk,
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input logic rst,
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input logic[31:0] pc_in,
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output logic[31:0] pc_out
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);
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reg[31:0] pc_curr;
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initial begin
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pc_curr = 32'hBFC00000;
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end : initial
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always_comb begin
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if (rst) begin
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pc_curr = 32'hBFC00000;
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end
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pc_out = pc_curr;
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end
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always_ff @(posedge clk) begin
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pc_curr <= pc_in;
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end
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endmodule : pc |