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127 lines
4 KiB
Verilog
127 lines
4 KiB
Verilog
/* Questions/Todos:
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-how to implement mult signed vs unsigned?
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-Need to clarify How many ALU ctrl flags there are
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-Need to go through & check special cases for each instruction
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-In the process of manually checking if every instruction has been accounted for in the actual enum
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-Right what your final set of different opeators each do (easy but somewhat tedious) :(
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*/
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module mips_cpu_alu(
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input logic[31:0] A, B,//alu_in1, alu_in2 -The two ALU inputs
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input logic [5:0] ALUFlags, //Output from ALU control - 6bits as there are 48 different instructions in our ISA that we need to implement
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/* The ALU Flags is 6 bits for now update when reduced */
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output logic ALUZero, //Is the output of the ALU 0? - used to check result
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output logic[31:0] ALUOut, // The ouput of the ALU
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);
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/*
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I have listed all of the instructions - reducing this set to figure out the size
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of ALUFlag/enum also need to go through the IS again and find special cases
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(like over/underflow) for each instruction & to note them
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i.e. for the instruction SLT (set on less than):
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ALUOut is '32'h000000001' if A < B
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*/
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// Instructions commented out have been accounted for
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/* Using an enum to define constants */
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//typedef enum logic[5:0] {
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//ADDIU = 6'd0, //Add immediate unsigned (no overflow)
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//ADDU = 6'd1, //Add unsigned (no overflow)
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//AND = 6'd2, //Bitwise and
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//ANDI = 6'd3, //Bitwise and immediate
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BEQ = 6'd4, //Branch on equal
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BGEZ = 6'd5, //Branch on greater than or equal to zero
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BGEZAL = 6'd6, //Branch on non-negative (>=0) and link
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BGTZ = 6'd7, //Branch on greater than zero
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BLEZ = 6'd8, //Branch on less than or equal to zero
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BLTZ = 6'd9, //Branch on less than zero
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BLTZAL = 6'd10, //Branch on less than zero and link
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BNE = 6'd11, //Branch on not equal
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//DIV = 6'd12, //Divide
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//DIVU = 6'd13, //Divide unsigned
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J = 6'd14, //Jump
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JALR = 6'd15, //Jump and link register
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JAL = 6'd16, //Jump and link
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JR = 6'd17, //Jump register
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LB = 6'd18, //Load byte
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LBU = 6'd19, //Load byte unsigned
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LH = 6'd20, //Load half-word
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LHU = 6'd21, //Load half-word unsigned
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LUI = 6'd22, //Load upper immediate
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LW = 6'd23, //Load word
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LWL = 6'd24, //Load word left
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LWR = 6'd25, //Load word right
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MTHI = 6'd26, //Move to HI
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MTLO = 6'd27, //Move to LO
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//MULT = 6'd28, //Multiply
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//MULTU = 6'd29, //Multiply unsigned
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//OR = 6'd30, //Bitwise or
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//ORI = 6'd31, //Bitwise or immediate
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SB = 6'd32, //Store byte
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SH = 6'd33, //Store half-word
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SLL = 6'd34, //Shift left logical
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SLLV = 6'd35, //Shift left logical variable
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SLT = 6'd36, //Set on less than (signed)
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SLTI = 6'd37, //Set on less than immediate (signed)
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SLTIU = 6'd38, //Set on less than immediate unsigned
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SLTU = 6'd39, //Set on less than unsigned
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SRA = 6'd40, //Shift right arithmetic
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SRAV = 6'd41, //Shift right arithmetic
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SRL = 6'd42, //Shift right logical
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SRLV = 6'd43, //Shift right logical variable
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//SUBU = 6'd44, //Subtract unsigned
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SW = 6'd45, //Store word
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XOR = 6'd46, //Bitwise exclusive or
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XORI = 6'd47, //Bitwise exclusive or immediate
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//} ALUFlags;
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/* This is how I believe our ctrl flags should be arranged */
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typedef enum logic [/* ? */ : 0]{
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ADD =
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SUB =
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MULT =
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DIV =
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//logical
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AND = 'd
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OR = 'd
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SLL = 'd
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} ALUFlags;
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always @(alu_in1, alu_in2, ALUFlags)
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begin
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case(ALUFlags)
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ADD: begin
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ALUOut = A & B; // is it = or <= ??
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end
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OR: begin
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ALUOut = A | B;
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end
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SLL: begin
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ALUOut = b >> shamt //Shamt is instruction read data [10:6]
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end
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end
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endmodule |