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https://github.com/supleed2/ELEC50010-IAC-CW.git
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312 lines
3.5 KiB
Plaintext
312 lines
3.5 KiB
Plaintext
== Instruction ==
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C code
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Assembly code
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Hex code
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Reference Output
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================
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ADDIU Add immediate unsigned (no overflow)
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== ADDU Add unsigned (no overflow) ==
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int main(void) {
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int a = 3 + 5;
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}
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ORI $4,$0,3
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ORI $5,$0,5
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ADDU $2,$4,$5
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JR $0
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34040003
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34050005
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00851021
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00000008
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register_v0 = 8
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AND Bitwise and
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ANDI Bitwise and immediate
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==BEQ Branch on equal==
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ORI $4,$0,5
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ORI $5,$0,5
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BEQ $4,$5,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040005
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34050005
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1085FFFF
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BGEZ Branch on greater than or equal to zero==
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ORI $4,$0,3
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BGEZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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04810003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BGEZAL Branch on non-negative (>=0) and link==
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ORI $4,$0,3
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BGEZAL $4,4
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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34040003
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04910004
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00000000
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24420001
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00000008
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00000000
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34020001
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03E00008
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register_v0 = 2
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==BGTZ Branch on greater than zero==
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ORI $4,$0,3
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BGTZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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1C800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLEZ Branch on less than or equal to zero==
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ORI $4,$0,-1
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BLEZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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3404FFFF
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18800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLTZ Branch on less than zero==
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ORI $4,$0,-1
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BLTZ $4,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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3404FFFF
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04800003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==BLTZAL Branch on less than zero and link==
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ORI $4,$0,-1
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BLTZAL $4,4
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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3404FFFF
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04900004
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00000000
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24420001
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00000000
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00000008
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34020001
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03E00008
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register_v0 = 2
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==BNE Branch on not equal==
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ORI $4,$0,3
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ORI $5,$0,5
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BNE $4,$5,3
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34040003
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34040005
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14850003
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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DIV Divide
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DIVU Divide unsigned
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==J Jump==
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J 4
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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08000004
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00000000
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00000008
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00000000
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34020001
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00000008
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register_v0 = 1
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==JALR Jump and link register==
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ORI $5,$0,1C
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LUI $5,BFC0
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JALR $4,$5
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $4
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3405001C
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3C05BCF0
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00A02009
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00000000
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24420001
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00000008
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00000000
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34020001
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00800008
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24C60000
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register_v0 = 2
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==JAL Jump and link==
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JAL 5
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NOP
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ADDIU $2,$2,1
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JR $0
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NOP
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ORI $2,$0,1
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JR $31
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0C000005
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00000000
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24420001
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00000008
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00000000
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34020001
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03E00008
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register_v0 = 2
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==JR Jump register==
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ORI $5,$0,14
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LUI $5,BFC0
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JR $5
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NOP
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JR $0
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NOP
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ORI $2,$0,1
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JR $0
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34050014
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3C05BCF0
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00A00008
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00000000
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00000008
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34020001
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00000008
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register_v0 = 1
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LB Load byte
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LBU Load byte unsigned
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LH Load half-word
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LHU Load half-word unsigned
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LUI Load upper immediate
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LW Load word
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LWL Load word left
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LWR Load word right
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MTHI Move to HI
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MTLO Move to LO
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MULT Multiply
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MULTU Multiply unsigned
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OR Bitwise or
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ORI Bitwise or immediate
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SB Store byte
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SH Store half-word
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SLL Shift left logical
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SLLV Shift left logical variable
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SLT Set on less than (signed)
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SLTI Set on less than immediate (signed)
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SLTIU Set on less than immediate unsigned
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SLTU Set on less than unsigned
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SRA Shift right arithmetic
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SRAV Shift right arithmetic
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SRL Shift right logical
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SRLV Shift right logical variable
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SUBU Subtract unsigned
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SW Store word
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XOR Bitwise exclusive or
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XORI Bitwise exclusive or immediate
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