mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-12-23 05:45:47 +00:00
27 lines
392 B
Verilog
27 lines
392 B
Verilog
module mips_cpu_npc(
|
|
input logic clk,
|
|
input logic rst,
|
|
input logic[31:0] npc_in,
|
|
output logic[31:0] npc_out
|
|
);
|
|
|
|
reg[31:0] npc_curr;
|
|
|
|
initial begin
|
|
npc_curr = (32'hBFC00000 + 32'd4);
|
|
end // initial
|
|
|
|
always_comb begin
|
|
if (rst) begin
|
|
npc_curr = (32'hBFC00000 + 32'd4);
|
|
end else begin
|
|
npc_curr = npc_in;
|
|
end
|
|
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
npc_out <= npc_curr;
|
|
end
|
|
|
|
endmodule // pc
|