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43 lines
616 B
Verilog
43 lines
616 B
Verilog
module ProgramCounter(
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input logic rst,
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input logic clk,
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input logic[31:0] pcWriteAddr,
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input logic pcWriteEn,
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output logic[31:0] pcRes,
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);
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logic[31:0] pcIncr;
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initial begin
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pcRes <= 32'h00000000;
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end
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always_comb begin
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pcIncr = pcRes + 32'h00000004
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end
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always @(posedge clk)
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begin
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if (rst == 1)
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begin
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pcRes <= 32'h00000000;
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end
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else
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begin
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if (pcWriteEn == 1) begin
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pcRes <= pcWriteAddr;
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end
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else begin
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pcRes <= pcIncr;
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end
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end
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$display("pc = %h",pcRes);
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end
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endmodule |