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100 lines
3.5 KiB
Verilog
100 lines
3.5 KiB
Verilog
module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave)
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input logic clk,
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input logic reset,
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input logic[31:0] address,
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input logic write,
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input logic read,
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output logic waitrequest,
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input logic[31:0] writedata,
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input logic[3:0] byteenable,
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output logic[31:0] readdata
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);
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parameter INSTR_INIT_FILE = "";
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parameter DATA_INIT_FILE = "";
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logic [31:0] data_memory [0:63]; // location 0x00001000 onwards
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logic [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards
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initial begin
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for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default
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data_memory[i] = 0;
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end
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for (integer i=0; i<$size(instr_memory); i++) begin //Initialise instr to zero by default
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instr_memory[i] = 0;
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end
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if (INSTR_INIT_FILE != "") begin //Load instr contents from file if specified
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$display("RAM: Loading RAM contents from %s", INSTR_INIT_FILE);
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$readmemh(INSTR_INIT_FILE, instr_memory);
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end
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for (integer i = 0; i<$size(instr_memory); i++) begin //Read out instr contents to log
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$display("byte +%h: %h", 32'hBFC00000+i*4, instr_memory[i]);
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end
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if (DATA_INIT_FILE != "") begin //Load data contents from file if specified
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$display("MEM: Loading MEM contents from %s", DATA_INIT_FILE);
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$readmemh(DATA_INIT_FILE, data_memory);
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end else begin
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$display("MEM FILE NOT GIVEN");
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end
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for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log
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$display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]);
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end
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waitrequest = 1'b0; // set waitrequest low to begin
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readdata = 32'h00000000; // set readdata low to begin
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end
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always_comb begin
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if (reset) begin
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waitrequest = 1'b0;
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end
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end
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always_ff @(posedge read or posedge write) begin
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waitrequest <= 1'b1;
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end
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always_ff @(posedge clk) begin
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if (waitrequest) begin
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if (read) begin
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if (address >= 32'hBFC00000) begin // instruction read
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readdata <= instr_memory[{address-32'hBFC00000}>>2];
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end else if (address >= 32'h00001000) begin // data read
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readdata <= data_memory[{address-32'h00001000}>>2];
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end
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waitrequest <= 1'b0; // end with setting waitrequest low
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end else if (write) begin
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if (address >= 32'hBFC00000) begin // writing to instr mem area is invalid
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$display("Error, write attempted in instr area at address: %h", address);
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end else if (address >= 32'h00001000) begin // write to data mem
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if (byteenable[3]) begin // if first byte enabled, write
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data_memory[{address-32'h00001000}>>2][31:24] <= writedata[31:24];
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end
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if (byteenable[2]) begin // if second byte enabled, write
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data_memory[{address-32'h00001000}>>2][23:16] <= writedata[23:16];
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end
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if (byteenable[1]) begin // if third byte enabled, write
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data_memory[{address-32'h00001000}>>2][15:8] <= writedata[15:8];
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end
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if (byteenable[0]) begin // if fourth byte enabled, write
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data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0];
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end
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waitrequest <= 1'b0; // end with setting waitrequest low
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end
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end else begin
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waitrequest <= 1'bx;
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readdata <= 32'hxxxxxxxx;
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end
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end else begin
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waitrequest <= 1'b0;
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readdata <= 32'h00000000;
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end
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end
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endmodule |