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53 lines
1 KiB
Verilog
53 lines
1 KiB
Verilog
module mips_cpu_pc(
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input logic clk,
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input logic rst,
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input logic[31:0] Instr,
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input logic[31:0] JumpReg,
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input logic[1:0] pc_ctrl,
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output logic[31:0] pc_out,
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output logic active
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);
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logic[31:0] out_cpc_out;
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logic[31:0] out_npc_out;
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logic[31:0] in_npc_in;
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assign pc_out = out_cpc_out;
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always @(*) begin
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case(pc_ctrl)
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2'd0: begin
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in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
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end
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2'd1: begin
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in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
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end
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2'd2: begin
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in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
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end
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2'd3: begin
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in_npc_in = JumpReg;
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end
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endcase
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end
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mips_cpu_cpc cpc(
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//Inputs for cpc
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.clk(clk),
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.rst(rst),
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.cpc_in(out_npc_out),
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//Outputs for cpc
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.cpc_out(out_cpc_out),
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.active(active)
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);
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mips_cpu_npc npc(
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//Inputs for npc
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.clk(clk),
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.rst(rst),
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.npc_in(in_npc_in),
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//Outputs for npc
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.npc_out(out_npc_out)
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);
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endmodule |