# -------------------------------------------------------------------------- # # # Copyright (C) 2019 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and any partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details, at # https://fpgasoftware.intel.com/eula. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition # Date created = 16:10:59 December 17, 2020 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # MIPS_CPU_Diagram_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE auto set_global_assignment -name TOP_LEVEL_ENTITY MIPS_CPU_Diagram set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:10:59 DECEMBER 17, 2020" set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name BDF_FILE MIPS_CPU_Diagram.bdf set_global_assignment -name BDF_FILE ALU.bdf set_global_assignment -name BDF_FILE CONTROL.bdf set_global_assignment -name BDF_FILE PC.bdf set_global_assignment -name BDF_FILE REGISTERS.bdf set_global_assignment -name BDF_FILE MUX_RegDst.bdf set_global_assignment -name BDF_FILE MUX_MemtoREg.bdf set_global_assignment -name BDF_FILE MUX_ALUSrc.bdf