mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-11-14 03:35:47 +00:00
Remove enum from alu.v using find&replace
This commit is contained in:
parent
76fbc7d5c4
commit
f56d61f2f3
|
@ -49,40 +49,6 @@ Alu Operations:
|
||||||
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef enum logic [4:0]{ //Enum list to use words instead of numbers when refering to operations.
|
|
||||||
|
|
||||||
ADD = 5'd0,
|
|
||||||
SUB = 5'd1,
|
|
||||||
MUL = 5'd2,//signed multiply
|
|
||||||
DIV = 5'd3,//signed divide
|
|
||||||
AND = 5'd4,
|
|
||||||
OR = 5'd5,
|
|
||||||
XOR = 5'd6,
|
|
||||||
SLL = 5'd7,
|
|
||||||
SLLV = 5'd8,
|
|
||||||
SRL = 5'd9,
|
|
||||||
SRLV = 5'd10,
|
|
||||||
SRA = 5'd11,
|
|
||||||
SRAV = 5'd12,
|
|
||||||
EQ = 5'd13,
|
|
||||||
LES = 5'd14,
|
|
||||||
LEQ = 5'd15,
|
|
||||||
GRT = 5'd16,
|
|
||||||
GEQ = 5'd17,
|
|
||||||
NEQ = 5'd18,
|
|
||||||
// PAS = 5'd19, no need for PAS as it was based on faulty reasoning that speical registers Hi and Lo are in the reg file.
|
|
||||||
SLT = 5'd20,//signed compare
|
|
||||||
SLTU = 5'd21,//unsigned compare
|
|
||||||
MULU = 5'd22,//unsigned multiply
|
|
||||||
DIVU = 5'd23,//unsigned divide
|
|
||||||
MTHI = 5'd24,
|
|
||||||
MTLO = 5'd25
|
|
||||||
|
|
||||||
|
|
||||||
} Ops;
|
|
||||||
|
|
||||||
Ops ALUOps; //Note confusing naming to avoid potential duplicate variable naming errors, as a result of enum implemetnation.
|
|
||||||
|
|
||||||
logic signed[63:0] SMulRes;//signed result of multiplication.
|
logic signed[63:0] SMulRes;//signed result of multiplication.
|
||||||
logic[63:0] UMulRes;//unsigned result of multiplication.
|
logic[63:0] UMulRes;//unsigned result of multiplication.
|
||||||
logic[31:0] temp_Hi;
|
logic[31:0] temp_Hi;
|
||||||
|
@ -100,64 +66,63 @@ initial begin
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(*) begin
|
always @(*) begin
|
||||||
assign ALUOps = ALUOp;
|
case(ALUOp)
|
||||||
case(ALUOps)
|
5'd0: begin
|
||||||
ADD: begin
|
|
||||||
ALURes = $signed(A) + $signed(B);
|
ALURes = $signed(A) + $signed(B);
|
||||||
end
|
end
|
||||||
|
|
||||||
SUB: begin
|
5'd1: begin
|
||||||
ALURes = $signed(A) - $signed(B);
|
ALURes = $signed(A) - $signed(B);
|
||||||
end
|
end
|
||||||
|
|
||||||
MUL: begin
|
5'd2: begin
|
||||||
SMulRes = $signed(A) * $signed(B);
|
SMulRes = $signed(A) * $signed(B);
|
||||||
temp_Hi = SMulRes[63:32];
|
temp_Hi = SMulRes[63:32];
|
||||||
temp_Lo = SMulRes[31:0];
|
temp_Lo = SMulRes[31:0];
|
||||||
end
|
end
|
||||||
|
|
||||||
DIV: begin
|
5'd3: begin
|
||||||
temp_Lo = $signed(A) / $signed(B);
|
temp_Lo = $signed(A) / $signed(B);
|
||||||
temp_Hi = $signed(A) % $signed(B);
|
temp_Hi = $signed(A) % $signed(B);
|
||||||
end
|
end
|
||||||
|
|
||||||
AND: begin
|
5'd4: begin
|
||||||
ALURes = A & B;
|
ALURes = A & B;
|
||||||
end
|
end
|
||||||
|
|
||||||
OR: begin
|
5'd5: begin
|
||||||
ALURes = A | B;
|
ALURes = A | B;
|
||||||
end
|
end
|
||||||
|
|
||||||
XOR: begin
|
5'd6: begin
|
||||||
ALURes = A^B;
|
ALURes = A^B;
|
||||||
end
|
end
|
||||||
|
|
||||||
SLL: begin
|
5'd7: begin
|
||||||
ALURes = B << shamt;
|
ALURes = B << shamt;
|
||||||
end
|
end
|
||||||
|
|
||||||
SLLV: begin
|
5'd8: begin
|
||||||
ALURes = B << A;
|
ALURes = B << A;
|
||||||
end
|
end
|
||||||
|
|
||||||
SRL: begin
|
5'd9: begin
|
||||||
ALURes = B >> shamt;
|
ALURes = B >> shamt;
|
||||||
end
|
end
|
||||||
|
|
||||||
SRLV: begin
|
5'd10: begin
|
||||||
ALURes = B >> A;
|
ALURes = B >> A;
|
||||||
end
|
end
|
||||||
|
|
||||||
SRA: begin
|
5'd11: begin
|
||||||
ALURes = $signed(B) >>> shamt;
|
ALURes = $signed(B) >>> shamt;
|
||||||
end
|
end
|
||||||
|
|
||||||
SRAV: begin
|
5'd12: begin
|
||||||
ALURes = $signed(B) >>> A;
|
ALURes = $signed(B) >>> A;
|
||||||
end
|
end
|
||||||
|
|
||||||
EQ: begin
|
5'd13: begin
|
||||||
if ($signed(A) == $signed(B)) begin
|
if ($signed(A) == $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -167,7 +132,7 @@ end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
LES: begin
|
5'd14: begin
|
||||||
if ($signed(A) < $signed(B)) begin
|
if ($signed(A) < $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -177,7 +142,7 @@ end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
LEQ: begin
|
5'd15: begin
|
||||||
if ($signed(A) <= $signed(B)) begin
|
if ($signed(A) <= $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -187,7 +152,7 @@ end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
GRT: begin
|
5'd16: begin
|
||||||
if ($signed(A) > $signed(B)) begin
|
if ($signed(A) > $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -197,7 +162,7 @@ end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
GEQ: begin
|
5'd17: begin
|
||||||
if ($signed(A) >= $signed(B)) begin
|
if ($signed(A) >= $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -207,7 +172,7 @@ end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
NEQ: begin
|
5'd18: begin
|
||||||
if ($signed(A) != $signed(B)) begin
|
if ($signed(A) != $signed(B)) begin
|
||||||
ALUCond = 1;
|
ALUCond = 1;
|
||||||
end
|
end
|
||||||
|
@ -221,7 +186,7 @@ end
|
||||||
ALURes = A;
|
ALURes = A;
|
||||||
end
|
end
|
||||||
*/
|
*/
|
||||||
SLT: begin
|
5'd20: begin
|
||||||
if ($signed(A) < $signed(B)) begin
|
if ($signed(A) < $signed(B)) begin
|
||||||
ALURes = 1;
|
ALURes = 1;
|
||||||
end
|
end
|
||||||
|
@ -230,7 +195,7 @@ end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
SLTU: begin
|
5'd21: begin
|
||||||
if (A < B) begin
|
if (A < B) begin
|
||||||
ALURes = 1;
|
ALURes = 1;
|
||||||
end
|
end
|
||||||
|
@ -239,22 +204,22 @@ end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
MULU: begin
|
5'd22: begin
|
||||||
UMulRes = A * B;
|
UMulRes = A * B;
|
||||||
temp_Hi = UMulRes[63:32];
|
temp_Hi = UMulRes[63:32];
|
||||||
temp_Lo = UMulRes[31:0];
|
temp_Lo = UMulRes[31:0];
|
||||||
end
|
end
|
||||||
|
|
||||||
DIVU: begin
|
5'd23: begin
|
||||||
temp_Lo = A / B;
|
temp_Lo = A / B;
|
||||||
temp_Hi = A % B;
|
temp_Hi = A % B;
|
||||||
end
|
end
|
||||||
|
|
||||||
MTHI: begin
|
5'd24: begin
|
||||||
temp_Hi = Hi_in;
|
temp_Hi = Hi_in;
|
||||||
end
|
end
|
||||||
|
|
||||||
MTLO: begin
|
5'd25: begin
|
||||||
temp_Lo = Lo_in;
|
temp_Lo = Lo_in;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue