Add initial coursework deliverables

rtl/mips_cpu_bus.v

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+module mips_cpu_bus(
+    /* Standard signals */
+    input logic clk,
+    input logic reset,
+    output logic active,
+    output logic[31:0] register_v0,
+
+    /* Avalon memory mapped bus controller (master) */
+    output logic[31:0] address,
+    output logic write,
+    output logic read,
+    input logic waitrequest,
+    output logic[31:0] writedata,
+    output logic[3:0] byteenable,
+    input logic[31:0] readdata
+);

rtl/mips_cpu_harvard.v

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+module mips_cpu_harvard(
+    /* Standard signals */
+    input logic clk,
+    input logic reset,
+    output logic active,
+    output logic [31:0] register_v0,
+
+    /* New clock enable. See below. */
+    input logic clk_enable,
+
+    /* Combinatorial read access to instructions */
+    output logic[31:0] instr_address,
+    input logic[31:0] instr_readdata,
+
+    /* Combinatorial read and single-cycle write access to instructions */
+    output logic[31:0] data_address,
+    output logic data_write,
+    output logic data_read,
+    output logic[31:0] data_writedata,
+    input logic[31:0] data_readdata
+);

test/test_mips_cpu_bus.sh

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+#!/bin/bash
+
+# should not create any files in the rtl dir
+# but auxiliary files / dirs can be utilised

test/test_mips_cpu_harvard.sh

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+#!/bin/bash
+
+# should not create any files in the rtl dir
+# but auxiliary files / dirs can be utilised