supleed2/ELEC50010-IAC-CW
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added div and instruction testcase and minor adjustment on bl instructions

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This commit is contained in:
yhp19 2020-12-10 13:51:54 +08:00
parent 0be5617371
commit db344b3150
4 changed files with 60 additions and 18 deletions
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2
inputs/blez.txt
View file

@ -1,4 +1,4 @@
3404FFFF 3C05FFFF
18800003 18800003
00000000 00000000
00000008 00000008

2
inputs/bltz.txt
View file

@ -1,4 +1,4 @@
3404FFFF 3C05FFFF
04800003 04800003
00000000 00000000
00000008 00000008

2
inputs/bltzal.txt
View file

@ -1,4 +1,4 @@
3404FFFF 3C05FFFF
04900004 04900004
00000000 00000000
24420001 24420001

72
inputs/reference.txt
View file

@ -25,8 +25,25 @@ JR $0
register_v0 = 8 register_v0 = 8
AND Bitwise and ==AND Bitwise and==
ANDI Bitwise and immediate
ORI $5,$0,0xCCCC
LUI $5,0xCCCC
ORI $4,$0,0xAAAA
LUI $4,0xAAAA
AND $2,$4,$5
JR $0
register_v0 = 0x88888888
==ANDI Bitwise and immediate==
ORI $4,$0,0xAAAA
LUI $4,0xAAAA
ANDI $2,$4,0xCCCC
JR $0
register_v0 = 0x00008888
==BEQ Branch on equal== ==BEQ Branch on equal==
@ -114,7 +131,7 @@ register_v0 = 1
==BLEZ Branch on less than or equal to zero== ==BLEZ Branch on less than or equal to zero==
ORI $4,$0,-1 LUI $4,0xFFFF
BLEZ $4,3 BLEZ $4,3
NOP NOP
JR $0 JR $0
@ -122,7 +139,7 @@ NOP
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
3404FFFF 3C05FFFF
18800003 18800003
00000000 00000000
00000008 00000008
@ -134,7 +151,7 @@ register_v0 = 1
==BLTZ Branch on less than zero== ==BLTZ Branch on less than zero==
ORI $4,$0,-1 LUI $4,0xFFFF
BLTZ $4,3 BLTZ $4,3
NOP NOP
JR $0 JR $0
@ -142,7 +159,7 @@ NOP
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
3404FFFF 3C05FFFF
04800003 04800003
00000000 00000000
00000008 00000008
@ -154,7 +171,7 @@ register_v0 = 1
==BLTZAL Branch on less than zero and link== ==BLTZAL Branch on less than zero and link==
ORI $4,$0,-1 LUI $4,0xFFFF
BLTZAL $4,4 BLTZAL $4,4
NOP NOP
ADDIU $2,$2,1 ADDIU $2,$2,1
@ -163,7 +180,7 @@ NOP
ORI $2,$0,1 ORI $2,$0,1
JR $31 JR $31
3404FFFF 3C05FFFF
04900004 04900004
00000000 00000000
24420001 24420001
@ -196,10 +213,32 @@ JR $0
register_v0 = 1 register_v0 = 1
DIV Divide ==DIV Divide== //May need other testcases for -ve/+ve, -ve/-ve
DIVU Divide unsigned
ORI $4,$0,3
ORI $5,$0,9
DIV $5,$4
MFHI $4
MFLO $5
ADDU $2,$4,$5
JR $0
register_v0 = 3
==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
LUI $4,0x8000
ORI $5,$0,2
DIV $4,$5
MFHI $4
MFLO $5
ADDU $2,$4,$5
JR $0
register_v0 = 0x40000000
==J Jump== ==J Jump==
J 4 J 4
NOP NOP
JR $0 JR $0
@ -217,8 +256,9 @@ JR $0
register_v0 = 1 register_v0 = 1
==JALR Jump and link register== ==JALR Jump and link register==
ORI $5,$0,1C
LUI $5,BFC0 ORI $5,$0,0x001C
LUI $5,0xBFC0
JALR $4,$5 JALR $4,$5
NOP NOP
ADDIU $2,$2,1 ADDIU $2,$2,1
@ -241,6 +281,7 @@ JR $4
register_v0 = 2 register_v0 = 2
==JAL Jump and link== ==JAL Jump and link==
JAL 5 JAL 5
NOP NOP
ADDIU $2,$2,1 ADDIU $2,$2,1
@ -260,8 +301,9 @@ JR $31
register_v0 = 2 register_v0 = 2
==JR Jump register== ==JR Jump register==
ORI $5,$0,14
LUI $5,BFC0 ORI $5,$0,0x0014
LUI $5,0xBFC0
JR $5 JR $5
NOP NOP
JR $0 JR $0
@ -316,7 +358,7 @@ LWR Load word right
//SLTU Set on less than unsigned //SLTU Set on less than unsigned
///SRA Shift right arithmetic //SRA Shift right arithmetic
//SRAV Shift right arithmetic //SRAV Shift right arithmetic