From 7e6bc7c3700c50bb39424eb73a97ed2b5244a4ca Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Wed, 9 Dec 2020 23:21:45 +0900
Subject: [PATCH 01/15] Update branch testcases

Reference file is not updated
---
 inputs/beq.txt    | 14 +++++++-------
 inputs/bgez.txt   | 12 ++++++------
 inputs/bgezal.txt | 14 +++++++-------
 inputs/bgtz.txt   | 12 ++++++------
 inputs/blez.txt   | 12 ++++++------
 inputs/bltz.txt   | 12 ++++++------
 inputs/bltzal.txt | 14 +++++++-------
 inputs/bne.txt    | 14 +++++++-------
 8 files changed, 52 insertions(+), 52 deletions(-)

diff --git a/inputs/beq.txt b/inputs/beq.txt
index f530cb6..4c4b4b7 100644
--- a/inputs/beq.txt
+++ b/inputs/beq.txt
@@ -1,7 +1,7 @@
-50004043
-50005043
-20005801
-00006C42
-80000000
-10002043
-80000000
+34040005
+34050005
+10850002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bgez.txt b/inputs/bgez.txt
index b548261..39e4c91 100644
--- a/inputs/bgez.txt
+++ b/inputs/bgez.txt
@@ -1,6 +1,6 @@
-30004043
-20001840
-00006C42
-80000000
-10002043
-80000000
+34040003
+04810002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bgezal.txt b/inputs/bgezal.txt
index 9b38b33..572f8d1 100644
--- a/inputs/bgezal.txt
+++ b/inputs/bgezal.txt
@@ -1,7 +1,7 @@
-30004043
-30001940
-00006C42
-10002442
-80000000
-10002043
-80000000
+34040003
+04910003
+24C60000
+24420001
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bgtz.txt b/inputs/bgtz.txt
index ec9fef1..862bcaf 100644
--- a/inputs/bgtz.txt
+++ b/inputs/bgtz.txt
@@ -1,6 +1,6 @@
-30004043
-200008C1
-00006C42
-80000000
-10002043
-80000000
+34040003
+1C800002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/blez.txt b/inputs/blez.txt
index 5bcbe25..d838ca0 100644
--- a/inputs/blez.txt
+++ b/inputs/blez.txt
@@ -1,6 +1,6 @@
-FFFF4043
-20000881
-00006C42
-80000000
-10002043
-80000000
+3404FFFF
+18800002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bltz.txt b/inputs/bltz.txt
index 0270f40..f8fe848 100644
--- a/inputs/bltz.txt
+++ b/inputs/bltz.txt
@@ -1,6 +1,6 @@
-FFFF4043
-20000840
-00006C42
-80000000
-10002043
-80000000
+3404FFFF
+04800002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bltzal.txt b/inputs/bltzal.txt
index 432027d..557625d 100644
--- a/inputs/bltzal.txt
+++ b/inputs/bltzal.txt
@@ -1,7 +1,7 @@
-FFFF4043
-20000940
-00006C42
-10002442
-80000000
-10002043
-80000000
+3404FFFF
+04900002
+24C60000
+24420001
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/bne.txt b/inputs/bne.txt
index f99f9c8..ee482bd 100644
--- a/inputs/bne.txt
+++ b/inputs/bne.txt
@@ -1,7 +1,7 @@
-30004043
-50005043
-20005841
-00006C42
-80000000
-10002043
-80000000
+34040003
+34050005
+14850002
+24C60000
+00000008
+34020001
+00000008
\ No newline at end of file

From b17158489fd7cb61a11492e717e251d31f1900be Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 10 Dec 2020 00:10:38 +0800
Subject: [PATCH 02/15] Added jump type testcase in ref.txt

---
 inputs/reference.txt | 327 ++++++++++++++++++++++++++-----------------
 1 file changed, 202 insertions(+), 125 deletions(-)

diff --git a/inputs/reference.txt b/inputs/reference.txt
index b7ae581..b276b2b 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -1,124 +1,124 @@
-== Instruction ==
-C code
-Assembly code
-Hex code
-Reference Output
-================
-
-== ADDIU Add immediate unsigned (no overflow) ==
-
-
-
-== ADDU Add unsigned (no overflow) ==
-
-int main(void) {
-    int a = 3 + 5;
-}
-
-ORI $4,$0,3
-ORI $5,$0,5
-ADDU $2,$4,$5
-JR $0
-
-34040003
-34050005
-00851021
-00000008
-
-register_v0 = 8
-
-
-== AND Bitwise and ==
-
-ANDI Bitwise and immediate
-
-==BEQ	Branch on equal==
-
+== Instruction ==
+C code
+Assembly code
+Hex code
+Reference Output
+================
+
+== ADDIU Add immediate unsigned (no overflow) ==
+
+
+
+== ADDU Add unsigned (no overflow) ==
+
+int main(void) {
+    int a = 3 + 5;
+}
+
+ORI $4,$0,3
+ORI $5,$0,5
+ADDU $2,$4,$5
+JR $0
+
+34040003
+34050005
+00851021
+00000008
+
+register_v0 = 8
+
+
+== AND Bitwise and ==
+
+ANDI Bitwise and immediate
+
+==BEQ	Branch on equal==
+
 ORI $4,$0,5
 ORI $5,$0,5
 BEQ $4,$5,2
 ADDIU $6,$6,0 
 JR $0
 ORI $2,$0,1
-JR $0
-
+JR $0
+
 50004043
 50005043
 20005801
 00006C42
 80000000
 10002043
-80000000
-
+80000000
+
 register_v0 = 1
 
-
-==BGEZ Branch on greater than or equal to zero==
-
+
+==BGEZ Branch on greater than or equal to zero==
+
 ORI $4,$0,3
 BGEZ $4,2
 ADDIU $6,$6,0
 JR $0
 ORI $2,$0,1
-JR $0
-
+JR $0
+
 30004043
 20001840
 00006C42
 80000000
 10002043
-80000000
-
-register_v0 = 1
-
-==BGEZAL Branch on non-negative (>=0) and link==
-
+80000000
+
+register_v0 = 1
+
+==BGEZAL Branch on non-negative (>=0) and link==
+
 ORI $4,$0,3
 BGEZAL $4,3
 ADDIU $6,$6,0
 ADDIU $2,$2,1
 JR $0
 ORI $2,$0,1
-JR $31
-
+JR $31
+
 30004043
 30001940
 00006C42
 10002442
 80000000
 10002043
-80000000
-
-register_v0 = 2
+80000000
+
+register_v0 = 2
+
+
+==BGTZ Branch on greater than zero==
 
-
-==BGTZ Branch on greater than zero==
-
 ORI $4,$0,3
 BGTZ $4,2
 ADDIU $6,$6,0
 JR $0
 ORI $2,$0,1
-JR $0
-
+JR $0
+
 30004043
 200008C1
 00006C42
 80000000
 10002043
 80000000
-
-register_v0 = 1
-
-==BLEZ Branch on less than or equal to zero==
-
+
+register_v0 = 1
+
+==BLEZ Branch on less than or equal to zero==
+
 ORI $4,$0,-1
 BLEZ $4,2
 ADDIU $6,$6,0
 JR $0
 ORI $2,$0,1
-JR $0
-
+JR $0
+
 FFFF4043
 20000881
 00006C42
@@ -126,56 +126,56 @@ FFFF4043
 10002043
 80000000
 
-register_v0 = 1
-
-==BLTZ Branch on less than zero==
-
+register_v0 = 1
+
+==BLTZ Branch on less than zero==
+
 ORI $4,$0,-1
 BLTZ $4,2
 ADDIU $6,$6,0
 JR $0
 ORI $2,$0,1
-JR $0
-
+JR $0
+
 FFFF4043
 20000840
 00006C42
 80000000
 10002043
-80000000
-
+80000000
+
 register_v0 = 1
 
-==BLTZAL	Branch on less than zero and link==
-
+==BLTZAL	Branch on less than zero and link==
+
 ORI $4,$0,-1
 BLTZAL $4,3
 ADDIU $6,$6,0
 ADDIU $2,$2,1
 JR $0
 ORI $2,$0,1
-JR $31
-
+JR $31
+
 FFFF4043
 20000940
 00006C42
 10002442
 80000000
 10002043
-80000000
-
+80000000
+
 register_v0 = 2
 
-==BNE	Branch on not equal==
-
+==BNE	Branch on not equal==
+
 ORI $4,$0,3
 ORI $5,$0,5
 BNE $4,$5,2
 ADDIU $6, $6, 0
 JR $0
 ORI $2,$0,1
-JR $
-
+JR $
+
 30004043
 50005043
 20005841
@@ -183,42 +183,119 @@ JR $
 80000000
 10002043
 80000000
-
-register_v0 = 1
-
-DIV	Divide
-DIVU	Divide unsigned
-J	Jump
-JALR	Jump and link register
-JAL	Jump and link
-JR	Jump register
-LB	Load byte
-LBU	Load byte unsigned
-LH	Load half-word
-LHU	Load half-word unsigned
-LUI	Load upper immediate
-LW	Load word
-LWL	Load word left
-LWR	Load word right
-MTHI	Move to HI
-MTLO	Move to LO
-MULT	Multiply
-MULTU	Multiply unsigned
-OR	Bitwise or
-ORI	Bitwise or immediate
-SB	Store byte
-SH	Store half-word
-SLL	Shift left logical
-SLLV	Shift left logical variable
-SLT	Set on less than (signed)
-SLTI	Set on less than immediate (signed)
-SLTIU	Set on less than immediate unsigned
-SLTU	Set on less than unsigned
-SRA	Shift right arithmetic
-SRAV	Shift right arithmetic
-SRL	Shift right logical
-SRLV	Shift right logical variable
-SUBU	Subtract unsigned
-SW	Store word
-XOR	Bitwise exclusive or
-XORI	Bitwise exclusive or immediate
\ No newline at end of file
+
+register_v0 = 1
+
+DIV	Divide
+DIVU	Divide unsigned
+
+==J	Jump==
+J 4
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+08000004
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==JALR	Jump and link register==
+ORI $5,$0,1C
+LUI $5,BFC0
+JALR $4,$5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $4
+
+3405001C
+3C05BCF0
+00A02009
+00000000
+24420001
+00000008
+00000000
+34020001
+00800008
+24C60000
+
+register_v0 = 2
+
+==JAL	Jump and link==
+JAL 5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+0C000005
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==JR	Jump register==
+ORI $5,$0,14
+LUI $5,BFC0  
+JR $5  
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34050014
+3C05BCF0
+00A00008
+00000000
+00000008
+34020001
+00000008
+
+register_v0 = 1
+
+LB	Load byte
+LBU	Load byte unsigned
+LH	Load half-word
+LHU	Load half-word unsigned
+LUI	Load upper immediate
+LW	Load word
+LWL	Load word left
+LWR	Load word right
+MTHI	Move to HI
+MTLO	Move to LO
+MULT	Multiply
+MULTU	Multiply unsigned
+OR	Bitwise or
+ORI	Bitwise or immediate
+SB	Store byte
+SH	Store half-word
+SLL	Shift left logical
+SLLV	Shift left logical variable
+SLT	Set on less than (signed)
+SLTI	Set on less than immediate (signed)
+SLTIU	Set on less than immediate unsigned
+SLTU	Set on less than unsigned
+SRA	Shift right arithmetic
+SRAV	Shift right arithmetic
+SRL	Shift right logical
+SRLV	Shift right logical variable
+SUBU	Subtract unsigned
+SW	Store word
+XOR	Bitwise exclusive or
+XORI	Bitwise exclusive or immediate

From 315e5af32c3046ab3fdc63cb741a4ada471333b5 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 10 Dec 2020 00:41:19 +0800
Subject: [PATCH 03/15] Update reference.txt

Fixed branch instruction test case in ref.txt
---
 inputs/reference.txt | 164 +++++++++++++++++++++++--------------------
 1 file changed, 87 insertions(+), 77 deletions(-)

diff --git a/inputs/reference.txt b/inputs/reference.txt
index b276b2b..8d21752 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -5,9 +5,7 @@ Hex code
 Reference Output
 ================
 
-== ADDIU Add immediate unsigned (no overflow) ==
-
-
+ADDIU Add immediate unsigned (no overflow) 
 
 == ADDU Add unsigned (no overflow) ==
 
@@ -27,142 +25,152 @@ JR $0
 
 register_v0 = 8
 
-
-== AND Bitwise and ==
-
+AND Bitwise and
 ANDI Bitwise and immediate
 
 ==BEQ	Branch on equal==
 
 ORI $4,$0,5
 ORI $5,$0,5
-BEQ $4,$5,2
-ADDIU $6,$6,0 
+BEQ $4,$5,3
+NOP 
 JR $0
+NOP
 ORI $2,$0,1
 JR $0
 
-50004043
-50005043
-20005801
-00006C42
-80000000
-10002043
-80000000
+34040005
+34050005
+1085FFFF
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 
-
 ==BGEZ Branch on greater than or equal to zero==
 
 ORI $4,$0,3
-BGEZ $4,2
-ADDIU $6,$6,0
+BGEZ $4,3
+NOP
 JR $0
+NOP
 ORI $2,$0,1
 JR $0
 
-30004043
-20001840
-00006C42
-80000000
-10002043
-80000000
+34040003
+04810003
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 
 ==BGEZAL Branch on non-negative (>=0) and link==
 
 ORI $4,$0,3
-BGEZAL $4,3
-ADDIU $6,$6,0
+BGEZAL $4,4
+NOP
 ADDIU $2,$2,1
 JR $0
+NOP
 ORI $2,$0,1
 JR $31
 
-30004043
-30001940
-00006C42
-10002442
-80000000
-10002043
-80000000
+34040003
+04910004
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
 
 register_v0 = 2
 
-
 ==BGTZ Branch on greater than zero==
 
 ORI $4,$0,3
-BGTZ $4,2
-ADDIU $6,$6,0
+BGTZ $4,3
+NOP
 JR $0
+NOP
 ORI $2,$0,1
 JR $0
 
-30004043
-200008C1
-00006C42
-80000000
-10002043
-80000000
+34040003
+1C800003
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 
 ==BLEZ Branch on less than or equal to zero==
 
 ORI $4,$0,-1
-BLEZ $4,2
-ADDIU $6,$6,0
+BLEZ $4,3
+NOP
 JR $0
+NOP
 ORI $2,$0,1
 JR $0
 
-FFFF4043
-20000881
-00006C42
-80000000
-10002043
-80000000
+3404FFFF
+18800003
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 
 ==BLTZ Branch on less than zero==
 
 ORI $4,$0,-1
-BLTZ $4,2
-ADDIU $6,$6,0
+BLTZ $4,3
+NOP
 JR $0
+NOP
 ORI $2,$0,1
 JR $0
 
-FFFF4043
-20000840
-00006C42
-80000000
-10002043
-80000000
+3404FFFF
+04800003
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 
 ==BLTZAL	Branch on less than zero and link==
 
 ORI $4,$0,-1
-BLTZAL $4,3
-ADDIU $6,$6,0
+BLTZAL $4,4
+NOP
 ADDIU $2,$2,1
 JR $0
+NOP
 ORI $2,$0,1
 JR $31
 
-FFFF4043
-20000940
-00006C42
-10002442
-80000000
-10002043
-80000000
+3404FFFF
+04900004
+00000000
+24420001
+00000000
+00000008
+34020001
+03E00008
 
 register_v0 = 2
 
@@ -170,19 +178,21 @@ register_v0 = 2
 
 ORI $4,$0,3
 ORI $5,$0,5
-BNE $4,$5,2
-ADDIU $6, $6, 0
+BNE $4,$5,3
+NOP
 JR $0
+NOP
 ORI $2,$0,1
-JR $
+JR $0
 
-30004043
-50005043
-20005841
-00006C42
-80000000
-10002043
-80000000
+34040003
+34040005
+14850003
+00000000
+00000008
+00000000
+34020001
+00000008
 
 register_v0 = 1
 

From 31ad264fac083cbf0a5271de877d02393c0256e6 Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Thu, 10 Dec 2020 00:57:31 +0800
Subject: [PATCH 04/15] updated with .txt files

---
 inputs/beq.txt       | 5 +++--
 inputs/bgez.txt      | 5 +++--
 inputs/bgezal.txt    | 7 ++++---
 inputs/bgtz.txt      | 7 ++++---
 inputs/blez.txt      | 5 +++--
 inputs/bltz.txt      | 5 +++--
 inputs/bltzal.txt    | 7 ++++---
 inputs/bne.txt       | 7 ++++---
 inputs/j.txt         | 6 ++++++
 inputs/jal.txt       | 7 +++++++
 inputs/jalr.txt      | 9 +++++++++
 inputs/jr.txt        | 7 +++++++
 inputs/reference.txt | 4 ++--
 13 files changed, 59 insertions(+), 22 deletions(-)
 create mode 100644 inputs/j.txt
 create mode 100644 inputs/jal.txt
 create mode 100644 inputs/jalr.txt
 create mode 100644 inputs/jr.txt

diff --git a/inputs/beq.txt b/inputs/beq.txt
index 4c4b4b7..88f0cfd 100644
--- a/inputs/beq.txt
+++ b/inputs/beq.txt
@@ -1,7 +1,8 @@
 34040005
 34050005
-10850002
-24C60000
+10850003
+00000000
 00000008
+00000000
 34020001
 00000008
\ No newline at end of file
diff --git a/inputs/bgez.txt b/inputs/bgez.txt
index 39e4c91..aae9c5c 100644
--- a/inputs/bgez.txt
+++ b/inputs/bgez.txt
@@ -1,6 +1,7 @@
 34040003
-04810002
-24C60000
+04810003
+00000000
 00000008
+00000000
 34020001
 00000008
\ No newline at end of file
diff --git a/inputs/bgezal.txt b/inputs/bgezal.txt
index 572f8d1..ce16a2b 100644
--- a/inputs/bgezal.txt
+++ b/inputs/bgezal.txt
@@ -1,7 +1,8 @@
 34040003
-04910003
-24C60000
+04910004
+00000000
 24420001
 00000008
+00000000
 34020001
-00000008
\ No newline at end of file
+03E00008
\ No newline at end of file
diff --git a/inputs/bgtz.txt b/inputs/bgtz.txt
index 862bcaf..46b5016 100644
--- a/inputs/bgtz.txt
+++ b/inputs/bgtz.txt
@@ -1,6 +1,7 @@
 34040003
-1C800002
-24C60000
+1C800003
+00000000
 00000008
+00000000
 34020001
-00000008
\ No newline at end of file
+00000008
diff --git a/inputs/blez.txt b/inputs/blez.txt
index d838ca0..d9b3a2e 100644
--- a/inputs/blez.txt
+++ b/inputs/blez.txt
@@ -1,6 +1,7 @@
 3404FFFF
-18800002
-24C60000
+18800003
+00000000
 00000008
+00000000
 34020001
 00000008
\ No newline at end of file
diff --git a/inputs/bltz.txt b/inputs/bltz.txt
index f8fe848..6623c71 100644
--- a/inputs/bltz.txt
+++ b/inputs/bltz.txt
@@ -1,6 +1,7 @@
 3404FFFF
-04800002
-24C60000
+04800003
+00000000
 00000008
+00000000
 34020001
 00000008
\ No newline at end of file
diff --git a/inputs/bltzal.txt b/inputs/bltzal.txt
index 557625d..a6be37c 100644
--- a/inputs/bltzal.txt
+++ b/inputs/bltzal.txt
@@ -1,7 +1,8 @@
 3404FFFF
-04900002
-24C60000
+04900004
+00000000
 24420001
+00000000
 00000008
 34020001
-00000008
\ No newline at end of file
+03E00008
\ No newline at end of file
diff --git a/inputs/bne.txt b/inputs/bne.txt
index ee482bd..4836f1a 100644
--- a/inputs/bne.txt
+++ b/inputs/bne.txt
@@ -1,7 +1,8 @@
 34040003
-34050005
-14850002
-24C60000
+34040005
+14850003
+00000000
 00000008
+00000000
 34020001
 00000008
\ No newline at end of file
diff --git a/inputs/j.txt b/inputs/j.txt
new file mode 100644
index 0000000..0043747
--- /dev/null
+++ b/inputs/j.txt
@@ -0,0 +1,6 @@
+08000004
+00000000
+00000008
+00000000
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/jal.txt b/inputs/jal.txt
new file mode 100644
index 0000000..f2e38d0
--- /dev/null
+++ b/inputs/jal.txt
@@ -0,0 +1,7 @@
+0C000005
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
\ No newline at end of file
diff --git a/inputs/jalr.txt b/inputs/jalr.txt
new file mode 100644
index 0000000..e4e33a8
--- /dev/null
+++ b/inputs/jalr.txt
@@ -0,0 +1,9 @@
+3405001C
+3C05BCF0
+00A02009
+00000000
+24420001
+00000008
+00000000
+34020001
+00800008
\ No newline at end of file
diff --git a/inputs/jr.txt b/inputs/jr.txt
new file mode 100644
index 0000000..b2a8045
--- /dev/null
+++ b/inputs/jr.txt
@@ -0,0 +1,7 @@
+34050014
+3C05BCF0
+00A00008
+00000000
+00000008
+34020001
+00000008
\ No newline at end of file
diff --git a/inputs/reference.txt b/inputs/reference.txt
index 8d21752..79d693f 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -41,7 +41,7 @@ JR $0
 
 34040005
 34050005
-1085FFFF
+10850003
 00000000
 00000008
 00000000
@@ -236,7 +236,7 @@ JR $4
 00000000
 34020001
 00800008
-24C60000
+
 
 register_v0 = 2
 

From 0be5617371239f8b012f1b8da7947a699cfab368 Mon Sep 17 00:00:00 2001
From: Ibrahim <ibzmo28@gmail.com>
Date: Wed, 9 Dec 2020 20:17:58 +0000
Subject: [PATCH 05/15] 75% done - need to redo arithemtic operation to test
 edge cases & do certain instr by hand

---
 inputs/ibrahimreference.txt | 274 ++++++++++++++++++++++++++++++++++++
 inputs/reference.txt        |  66 ++++++---
 inputs/sll.txt              |   3 +
 inputs/sllv.txt             |   4 +
 inputs/slti.txt             |   3 +
 inputs/sltiu.txt            |   3 +
 inputs/sltu.txt             |   4 +
 inputs/sra.txt              |   3 +
 inputs/srav.txt             |   4 +
 inputs/srl.txt              |   3 +
 inputs/srlv.txt             |   4 +
 inputs/subu.txt             |   4 +
 inputs/sw.txt               |   4 +
 inputs/xor.txt              |   4 +
 inputs/xori.txt             |   3 +
 15 files changed, 364 insertions(+), 22 deletions(-)
 create mode 100644 inputs/ibrahimreference.txt
 create mode 100644 inputs/sll.txt
 create mode 100644 inputs/sllv.txt
 create mode 100644 inputs/slti.txt
 create mode 100644 inputs/sltiu.txt
 create mode 100644 inputs/sltu.txt
 create mode 100644 inputs/sra.txt
 create mode 100644 inputs/srav.txt
 create mode 100644 inputs/srl.txt
 create mode 100644 inputs/srlv.txt
 create mode 100644 inputs/subu.txt
 create mode 100644 inputs/sw.txt
 create mode 100644 inputs/xor.txt
 create mode 100644 inputs/xori.txt

diff --git a/inputs/ibrahimreference.txt b/inputs/ibrahimreference.txt
new file mode 100644
index 0000000..64df695
--- /dev/null
+++ b/inputs/ibrahimreference.txt
@@ -0,0 +1,274 @@
+===== ADDIU ==========
+int main(void) {
+    int a = -2147483648 + -32768 ;
+}
+
+ORI $4,$0,-2147483648
+ADDIU $2,$4,-32768
+JR $0
+
+//used to check for overflow 32768 is 2^15 which should 
+be sign extended. 21... is 2^31 
+
+
+register_v0 = 
+
+==========XORI	Bitwise exclusive or immediate=============
+
+int main(void) {
+    int a = 5 ^ 2;
+}
+
+ori $4,$0,5
+xori $2,$4,2
+jr $0
+
+register 0 = 7
+
+34040005
+38820002
+00000008
+
+convert to little endian
+
+////////
+
+====XOR	Bitwise exclusive or==========
+
+int main(void) {
+    int a = 5 ^ 2;
+}
+
+ori $4, $0, 5
+ori $5, $0, 2
+xor $2, $4, $5
+jr $0
+
+register 0 = 7
+
+34040005
+34050002
+00851026
+00000008
+
+convert to little endian
+
+////////
+
+========SW	Store word==============
+
+int main(void) {
+
+
+ori $4, $0, 5 
+ori $5, $0, 1
+sw $4, 1($5)
+jr $0
+
+register 0 = 5
+
+34040005
+34050001
+aca40001
+00000008
+
+
+=========== SUBU	Subtract unsigned ===========
+
+int main(void) {
+    int a = 5-3;
+}
+
+ori $4,$0,5
+ori $5,$0,3
+subu $2,$4,$5
+jr $0
+
+
+register_v0 = 2
+
+
+34040005
+34050003
+00851023
+00000008
+
+
+========= SRLV	Shift right logical variable ======
+
+
+int main(void) {
+    int a = 2;
+    int b = 16>>a;
+}
+
+ori $4,$0,2
+ori $5,$0,16
+srlv $2,$5,$4
+jr $0
+
+register 0 = 3
+
+34040002
+34050010
+//////
+//////
+
+===============  SRL	Shift right logical  ==============
+
+
+int main(void) {
+    int a = -2147483647>>2; #logical shift - should feed in 0s
+}
+
+ori $4,$0,-2147483647
+srl $2,$4,$2
+jr $0
+
+register 0 = 536870912 (2^29)
+
+34040001
+00041002
+00000008
+
+========== SRAV	Shift right arithmetic variable =======
+
+int main(void) {
+    int a = 2;
+    int b = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
+}
+
+ori $4, $0, 2
+ori $5,$0,-2147483647
+srav $2,$5,$4
+jr $0
+
+register 0 = -536870912 (first 3 bits high - rest low)
+
+34040002
+34050001
+////////
+///////
+
+====== SRA	Shift right arithmetic ==========
+
+int main(void) {
+    int a = -2147483647>>2; #arithemtic shift not logical - feed in 1s (sign extension)
+}
+
+
+ori $4,$0,-2147483647
+sra $2,$4,$2
+jr $0
+
+register 0 = -536870912 (first 3 bits high - rest low)
+
+34040001
+00041003
+00000008
+
+======= SLTU	Set on less than unsigned =====
+
+int main() {
+    int a = 10;
+    int b = 9;
+
+    max = a < b ? 1 : 0;
+
+    return max;
+}
+
+
+ori $4, $0, 10
+ori $5, $0, 9
+sltu $2, $4, $5
+jr $0
+
+register 0 = 0
+
+3404000a
+34050009
+0085102b
+00000008
+
+=========== SLTIU	Set on less than immediate unsigned ==================
+
+int main() {
+    int a = 10;
+
+    max = a < 9 ? 1 : 0;
+
+    return max;
+}
+
+
+ori $4, $0, 10
+sltiu $2, $4, 9
+jr $0
+
+register 0 = 0
+
+3404000a
+2c820009
+00000008
+
+======= SLTI	Set on less than immediate (signed) ========
+
+int main() {
+    int a = 10;
+
+    max = a < 9 ? 1 : 0;
+
+    return max;
+}
+
+
+ori $4, $0, 10
+slti $2, $4, 9
+jr $0
+
+register 0 = 0
+
+3404000a
+28820009
+00000008
+
+
+
+======= SLLV	Shift left logical variable ======
+
+
+int main(void) {
+    int a = 2;
+    int b = 3<<a;
+}
+
+ori $4,$0,2
+ori $5,$0,3
+sllv $2,$5,$4
+jr $0
+
+register 0 = 16
+
+34040002
+34050003
+//////
+//////
+
+
+======= SLL	Shift left logical  ======
+
+
+int main(void) {
+    int a = 3<<2;
+}
+
+ori $4,$0,3
+sll $2,$4,2
+jr $0
+
+register 0 = 16
+
+34040003
+00041080
+00000008
\ No newline at end of file
diff --git a/inputs/reference.txt b/inputs/reference.txt
index 79d693f..d4690fb 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -287,25 +287,47 @@ LUI	Load upper immediate
 LW	Load word
 LWL	Load word left
 LWR	Load word right
-MTHI	Move to HI
-MTLO	Move to LO
-MULT	Multiply
-MULTU	Multiply unsigned
-OR	Bitwise or
-ORI	Bitwise or immediate
-SB	Store byte
-SH	Store half-word
-SLL	Shift left logical
-SLLV	Shift left logical variable
-SLT	Set on less than (signed)
-SLTI	Set on less than immediate (signed)
-SLTIU	Set on less than immediate unsigned
-SLTU	Set on less than unsigned
-SRA	Shift right arithmetic
-SRAV	Shift right arithmetic
-SRL	Shift right logical
-SRLV	Shift right logical variable
-SUBU	Subtract unsigned
-SW	Store word
-XOR	Bitwise exclusive or
-XORI	Bitwise exclusive or immediate
+
+//MTHI	Move to HI
+
+//MTLO	Move to LO
+
+//MULT	Multiply
+
+//MULTU	Multiply unsigned
+
+//OR	Bitwise or
+
+//ORI	Bitwise or immediate
+
+//SB	Store byte
+
+//SH	Store half-word
+
+//SLL	Shift left logical
+
+//SLLV	Shift left logical variable
+
+//SLT	Set on less than (signed)
+
+//SLTI	Set on less than immediate (signed)
+
+//SLTIU	Set on less than immediate unsigned
+
+//SLTU	Set on less than unsigned
+
+///SRA	Shift right arithmetic
+
+//SRAV	Shift right arithmetic
+
+//SRL	Shift right logical
+
+//SRLV	Shift right logical variable
+
+//SUBU	Subtract unsigned
+
+//SW	Store word
+
+//XOR	Bitwise exclusive or
+
+//XORI	Bitwise exclusive or immediate
diff --git a/inputs/sll.txt b/inputs/sll.txt
new file mode 100644
index 0000000..e03a5d2
--- /dev/null
+++ b/inputs/sll.txt
@@ -0,0 +1,3 @@
+34040003
+00041080
+00000008
\ No newline at end of file
diff --git a/inputs/sllv.txt b/inputs/sllv.txt
new file mode 100644
index 0000000..93c2eb4
--- /dev/null
+++ b/inputs/sllv.txt
@@ -0,0 +1,4 @@
+34040002
+34050003
+//////
+//////
\ No newline at end of file
diff --git a/inputs/slti.txt b/inputs/slti.txt
new file mode 100644
index 0000000..daf8c51
--- /dev/null
+++ b/inputs/slti.txt
@@ -0,0 +1,3 @@
+3404000a
+28820009
+00000008
\ No newline at end of file
diff --git a/inputs/sltiu.txt b/inputs/sltiu.txt
new file mode 100644
index 0000000..a601fcc
--- /dev/null
+++ b/inputs/sltiu.txt
@@ -0,0 +1,3 @@
+3404000a
+2c820009
+00000008
diff --git a/inputs/sltu.txt b/inputs/sltu.txt
new file mode 100644
index 0000000..438e8e3
--- /dev/null
+++ b/inputs/sltu.txt
@@ -0,0 +1,4 @@
+3404000a
+34050009
+0085102b
+00000008
\ No newline at end of file
diff --git a/inputs/sra.txt b/inputs/sra.txt
new file mode 100644
index 0000000..3ce15cf
--- /dev/null
+++ b/inputs/sra.txt
@@ -0,0 +1,3 @@
+34040001
+00041003
+00000008
diff --git a/inputs/srav.txt b/inputs/srav.txt
new file mode 100644
index 0000000..bb14f29
--- /dev/null
+++ b/inputs/srav.txt
@@ -0,0 +1,4 @@
+34040002
+34050001
+////////
+///////
\ No newline at end of file
diff --git a/inputs/srl.txt b/inputs/srl.txt
new file mode 100644
index 0000000..2c9ac5f
--- /dev/null
+++ b/inputs/srl.txt
@@ -0,0 +1,3 @@
+34040010
+00041002
+00000008
\ No newline at end of file
diff --git a/inputs/srlv.txt b/inputs/srlv.txt
new file mode 100644
index 0000000..fa1b6a4
--- /dev/null
+++ b/inputs/srlv.txt
@@ -0,0 +1,4 @@
+34040002
+34050010
+//////
+//////
\ No newline at end of file
diff --git a/inputs/subu.txt b/inputs/subu.txt
new file mode 100644
index 0000000..7c8a7eb
--- /dev/null
+++ b/inputs/subu.txt
@@ -0,0 +1,4 @@
+34040005
+34050003
+00851023
+00000008
\ No newline at end of file
diff --git a/inputs/sw.txt b/inputs/sw.txt
new file mode 100644
index 0000000..cdba78c
--- /dev/null
+++ b/inputs/sw.txt
@@ -0,0 +1,4 @@
+34040005
+34050001
+aca40001
+00000008
\ No newline at end of file
diff --git a/inputs/xor.txt b/inputs/xor.txt
new file mode 100644
index 0000000..46f4ec9
--- /dev/null
+++ b/inputs/xor.txt
@@ -0,0 +1,4 @@
+34040005
+34050002
+00851026
+00000008
\ No newline at end of file
diff --git a/inputs/xori.txt b/inputs/xori.txt
new file mode 100644
index 0000000..c4af2a8
--- /dev/null
+++ b/inputs/xori.txt
@@ -0,0 +1,3 @@
+34040005
+38820002
+00000008
\ No newline at end of file

From db344b3150aa0f8498b2c5bdcc9f576fb6265773 Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Thu, 10 Dec 2020 13:51:54 +0800
Subject: [PATCH 06/15] added div and instruction testcase and minor adjustment
 on bl instructions

---
 inputs/blez.txt      |  2 +-
 inputs/bltz.txt      |  2 +-
 inputs/bltzal.txt    |  2 +-
 inputs/reference.txt | 72 +++++++++++++++++++++++++++++++++++---------
 4 files changed, 60 insertions(+), 18 deletions(-)

diff --git a/inputs/blez.txt b/inputs/blez.txt
index d9b3a2e..7ce11a9 100644
--- a/inputs/blez.txt
+++ b/inputs/blez.txt
@@ -1,4 +1,4 @@
-3404FFFF
+3C05FFFF
 18800003
 00000000
 00000008
diff --git a/inputs/bltz.txt b/inputs/bltz.txt
index 6623c71..93100eb 100644
--- a/inputs/bltz.txt
+++ b/inputs/bltz.txt
@@ -1,4 +1,4 @@
-3404FFFF
+3C05FFFF
 04800003
 00000000
 00000008
diff --git a/inputs/bltzal.txt b/inputs/bltzal.txt
index a6be37c..6e01f55 100644
--- a/inputs/bltzal.txt
+++ b/inputs/bltzal.txt
@@ -1,4 +1,4 @@
-3404FFFF
+3C05FFFF
 04900004
 00000000
 24420001
diff --git a/inputs/reference.txt b/inputs/reference.txt
index d4690fb..c947c50 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -25,8 +25,25 @@ JR $0
 
 register_v0 = 8
 
-AND Bitwise and
-ANDI Bitwise and immediate
+==AND Bitwise and==
+
+ORI $5,$0,0xCCCC
+LUI $5,0xCCCC 
+ORI $4,$0,0xAAAA
+LUI $4,0xAAAA  
+AND  $2,$4,$5
+JR $0
+
+register_v0 = 0x88888888
+
+==ANDI Bitwise and immediate==
+
+ORI $4,$0,0xAAAA
+LUI $4,0xAAAA  
+ANDI  $2,$4,0xCCCC
+JR $0
+
+register_v0 = 0x00008888
 
 ==BEQ	Branch on equal==
 
@@ -114,7 +131,7 @@ register_v0 = 1
 
 ==BLEZ Branch on less than or equal to zero==
 
-ORI $4,$0,-1
+LUI $4,0xFFFF
 BLEZ $4,3
 NOP
 JR $0
@@ -122,7 +139,7 @@ NOP
 ORI $2,$0,1
 JR $0
 
-3404FFFF
+3C05FFFF
 18800003
 00000000
 00000008
@@ -134,7 +151,7 @@ register_v0 = 1
 
 ==BLTZ Branch on less than zero==
 
-ORI $4,$0,-1
+LUI $4,0xFFFF 
 BLTZ $4,3
 NOP
 JR $0
@@ -142,7 +159,7 @@ NOP
 ORI $2,$0,1
 JR $0
 
-3404FFFF
+3C05FFFF
 04800003
 00000000
 00000008
@@ -154,7 +171,7 @@ register_v0 = 1
 
 ==BLTZAL	Branch on less than zero and link==
 
-ORI $4,$0,-1
+LUI $4,0xFFFF 
 BLTZAL $4,4
 NOP
 ADDIU $2,$2,1
@@ -163,7 +180,7 @@ NOP
 ORI $2,$0,1
 JR $31
 
-3404FFFF
+3C05FFFF
 04900004
 00000000
 24420001
@@ -196,10 +213,32 @@ JR $0
 
 register_v0 = 1
 
-DIV	Divide
-DIVU	Divide unsigned
+==DIV	Divide== //May need other testcases for -ve/+ve, -ve/-ve
+
+ORI $4,$0,3
+ORI $5,$0,9
+DIV  $5,$4
+MFHI $4
+MFLO $5
+ADDU $2,$4,$5
+JR $0
+
+register_v0 = 3
+
+==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
+
+LUI $4,0x8000 
+ORI $5,$0,2
+DIV  $4,$5
+MFHI $4
+MFLO $5
+ADDU $2,$4,$5
+JR $0
+
+register_v0 = 0x40000000
 
 ==J	Jump==
+
 J 4
 NOP
 JR $0
@@ -217,8 +256,9 @@ JR $0
 register_v0 = 1
 
 ==JALR	Jump and link register==
-ORI $5,$0,1C
-LUI $5,BFC0
+
+ORI $5,$0,0x001C
+LUI $5,0xBFC0
 JALR $4,$5
 NOP
 ADDIU $2,$2,1
@@ -241,6 +281,7 @@ JR $4
 register_v0 = 2
 
 ==JAL	Jump and link==
+
 JAL 5
 NOP
 ADDIU $2,$2,1
@@ -260,8 +301,9 @@ JR $31
 register_v0 = 2
 
 ==JR	Jump register==
-ORI $5,$0,14
-LUI $5,BFC0  
+
+ORI $5,$0,0x0014
+LUI $5,0xBFC0  
 JR $5  
 NOP
 JR $0
@@ -316,7 +358,7 @@ LWR	Load word right
 
 //SLTU	Set on less than unsigned
 
-///SRA	Shift right arithmetic
+//SRA	Shift right arithmetic
 
 //SRAV	Shift right arithmetic
 

From c93473a54d1ba46d7d7400a4c37b06d84f5f282a Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Thu, 10 Dec 2020 17:24:40 +0900
Subject: [PATCH 07/15] Update test_mips_cpu_harvard.sh

Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)
---
 inputs/addu.ref.txt           |  1 +
 test/test_mips_cpu_harvard.sh | 43 ++++++++++++++++++++++-------------
 2 files changed, 28 insertions(+), 16 deletions(-)
 create mode 100644 inputs/addu.ref.txt

diff --git a/inputs/addu.ref.txt b/inputs/addu.ref.txt
new file mode 100644
index 0000000..301160a
--- /dev/null
+++ b/inputs/addu.ref.txt
@@ -0,0 +1 @@
+8
\ No newline at end of file
diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh
index 63cae06..3086986 100644
--- a/test/test_mips_cpu_harvard.sh
+++ b/test/test_mips_cpu_harvard.sh
@@ -1,11 +1,10 @@
 #!/bin/bash
 
-# should not create any files in the rtl dir
-# but auxiliary files / dirs can be utilised
-
+#**Delete command for windows before submission**
+#rm inputs/*.log.txt inputs/*.ref.txt
 
 # Source File & Source Directory Parsing
-SRC_DIR=${1?Error: no source directory given in argument};      # e.g. ./rtl
+SRC_DIR=${1?Error: no source directory given in argument};      # e.g. rtl
 SRC=$(ls ${SRC_DIR} | grep -E "harvard|memory|alu|regfile|pc|control");
 SRC_TEMP="";
 for src in ${SRC}
@@ -13,40 +12,52 @@ do
     SRC_TEMP+=${SRC_DIR}/${src}" ";
 done
 SRC=${SRC_TEMP}
-echo ${SRC}
 
 # Instruction Argument
 INSTR=${2:-"No instruction specified: running all testcases"};  # e.g. addiu
-echo ${INSTR};
 
 # Start Testing
 if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
 then
     # All Testcase Files
-    TESTCASES=$(ls ./inputs | grep ".txt");
-    echo ${TESTCASES}
+    TESTCASES=$(find ./inputs ! -name '*ref*'  ! -name '*log*' ! -name '*out*' ! -name 'inputs' | sed 's#.*/##');
+    #echo ${TESTCASES}
     for TESTCASE in ${TESTCASES}
     do
-    # Run Each Testcase File
-    echo ${TESTCASE}
-/mnt/c/Windows/System32/cmd.exe /C \
+        # Run Each Testcase File
+        TESTCASE="${TESTCASE%%.*}";
+        #echo ${TESTCASE};
+#/mnt/c/Windows/System32/cmd.exe /C \
 iverilog -Wall -g2012 \
     -s mips_cpu_harvard_tb \
     -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\" \
     -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
-    ${SRC}
-/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE};
+    ${SRC} 2> /dev/null
+/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${TESTCASE}.log.txt;       # log file for debugging (contains $display)
+echo "$(tail -1 ./inputs/${TESTCASE}.log.txt)" > ./inputs/${TESTCASE}.out.txt;                                       # register v0 output to compare with reference
+if diff -w ./inputs/${TESTCASE}.out.txt ./inputs/${TESTCASE}.ref.txt &> /dev/null                                    # compare
+then 
+    echo ${TESTCASE} ${TESTCASE} "Pass";
+else 
+    printf '%s %s %s%d %s%d%s\n' "${TESTCASE}" "${TESTCASE}" "Fail Output=" "$(tail -1 ./inputs/${TESTCASE}.out.txt)" "Ref=" "$(tail -1 ./inputs/${TESTCASE}.ref.txt)" 2> /dev/null;
+fi
     done
 
 else
     # Run Testcase File Of Specified Instruction
-    echo ${INSTR};
 /mnt/c/Windows/System32/cmd.exe /C \
 iverilog -Wall -g2012 \
     -s mips_cpu_harvard_tb \
     -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
     -o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
-    ${SRC}
-/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR};
+    ${SRC} 2> /dev/null
+/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR} &> ./inputs/${INSTR}.log.txt;            # log file for debugging (contains $display)
+echo "$(tail -1 ./inputs/${INSTR}.log.txt)" > ./inputs/${INSTR}.out.txt;                                            # register v0 output to compare with reference
+if diff -w ./inputs/${INSTR}.out.txt ./inputs/${INSTR}.ref.txt &> /dev/null                                         # compare
+then 
+    echo ${INSTR} ${INSTR} "Pass";
+else 
+    printf '%s %s %s%d %s%d%s\n' "${INSTR}" "${INSTR}" "Fail Output=" "$(tail -1 ./inputs/${INSTR}.out.txt)" "Ref=" "$(tail -1 ./inputs/${INSTR}.ref.txt)" 2> /dev/null;
 fi
 
+fi

From 84adff2ed126708020f66db4a9cb4cb8dd09efe7 Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Thu, 10 Dec 2020 19:14:16 +0900
Subject: [PATCH 08/15] Update memory

No longer need the massive memory
---
 rtl/mips_cpu_memory.v | 41 +++++++++++++----------------------------
 1 file changed, 13 insertions(+), 28 deletions(-)

diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index 45aa576..ee7544e 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -1,19 +1,3 @@
-/*  
-Memory for Harvard Interface
-- RAM Size: 32 x 2^32 = 32 x 4294967296
-- Instructions in binaries or hex -> RAM_INIT_FILE
-- combinatorial read/fetch of instruction via instr_ port
-- combinatorial read and single cycle write of data via data_ port
-
-Instantiation of Memory Module
-- mips_cpu_memory #(RAM_INIT_FILE) ramInst(clk, data_address, data_write, data_read, data_writedata, data_readdata, instr_address, instr_readdata);
-
-Special Memory Locations
-- Whether a particular address maps to RAM, ROM, or something else is entirely down to the top-level circuit outside your CPU.
-- special memory locations: 0x00000000 (CPU halt), 0xBFC00000 (start execution after reset)
-- PC should be 0xBFC00000 at the start and 0x00000000 at the end
-*/
-
 module mips_cpu_memory(
     input logic clk,
 
@@ -31,29 +15,32 @@ module mips_cpu_memory(
 );
     parameter RAM_INIT_FILE = "";
 
-    reg [31:0] memory [0:7];   // 2^30 set as 8 for now for small testcases
+    reg [31:0] data_memory [0:63];
+    reg [31:0] instr_memory [0:63];
 
     initial begin
         integer i;
         //Initialise to zero by default
-        for (i=0; i<8; i++) begin
-            memory[i]=0;
+        for (i=0; i<$size(data_memory); i++) begin
+            data_memory[i] = 0;
+        end
+        for (i=0; i<$size(instr_memory); i++) begin
+            instr_memory[i] = 0;
         end
         //Load contents from file if specified
         if (RAM_INIT_FILE != "") begin
             $display("RAM: Loading RAM contents from %s", RAM_INIT_FILE);
-            $readmemh(RAM_INIT_FILE, memory, 32'h4); //32'hBFC00000 equivalent for small memory as byte 16
+            $readmemh(RAM_INIT_FILE, instr_memory);
         end
 
-        //Display what's in memory for debugging
-        for (integer j = 0; j<$size(memory); j++) begin
-            $display("Byte %d, %h", j*4, memory[j]);
+        for (integer j = 0; j<$size(instr_memory); j++) begin
+            $display("byte +%h: %h", 32'hBFC00000+j*4, instr_memory[j]);
         end
     end
 
     //Combinatorial read path for data and instruction.
-    assign data_readdata = data_read ? {memory[data_address],memory[data_address+1],memory[data_address+2],memory[data_address+3]} : 16'hxxxx;
-    assign instr_readdata = memory[instr_address/4];
+    assign data_readdata = data_read ? data_memory[data_address>>2] : 32'hxxxxxxxx;
+    assign instr_readdata = (instr_address >= 32'hBFC00000 && instr_address < 32'hBFC00000+$size(instr_memory)) ? instr_memory[(instr_address-32'hBFC00000)>>2] : 32'hxxxxxxxx;
 
 
     //Synchronous write path
@@ -62,10 +49,8 @@ module mips_cpu_memory(
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read
-                memory[data_address] <= data_writedata;            
+                data_memory[data_address] <= data_writedata;            
             end
         end
     end
 endmodule
-
-

From 04b1ed4fed542d3b4b81a5cf6a2b887edbc96e29 Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Thu, 10 Dec 2020 22:27:08 +0900
Subject: [PATCH 09/15] Update control and memory

Fixed some errors when testing
---
 rtl/mips_cpu_control.v | 17 ++++++++---------
 rtl/mips_cpu_memory.v  |  2 +-
 2 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index f51c723..28198d1 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -83,9 +83,9 @@ assign rt = Instr[20:16];
 
 always @(*) begin
     //CtrlRegDst logic
-    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin //
+    if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
         CtrlRegDst = 2'd0; //Write address comes from rt
-    end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin//
+    end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
         CtrlRegDst = 2'd1; //Write address comes from rd
     end else if (op == JAL)begin
         CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
@@ -96,10 +96,10 @@ always @(*) begin
         CtrlPC = 2'd1; // Branches - Jumps relative to PC
     end else if((op==J) || (op==JAL))begin
         CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
-    end else if((op==JR) || (op==JALR))begin
+    end else if((funct==JR) || (funct==JALR))begin
         CtrlPC = 2'd3; // Jumps using Register.
-        $display("Ctrl PC Jump Register");
-    end else begin CtrlPC = 2'd0; $display("Ctrl PC No Jump/Branch");end // No jumps or branches, just increment to next word
+        //$display("Ctrl PC Jump Register");
+    end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
 
     //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
     if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin
@@ -115,7 +115,7 @@ always @(*) begin
     //CtrlALUOp Logic
     if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
         CtrlALUOp = 5'd0; //ADD from ALUOps
-    end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))
+    end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin
         CtrlALUOp = 5'd4;//AND from ALUOps
     end else if(op==BEQ) begin
         CtrlALUOp = 5'd13;//EQ from ALUOps
@@ -133,7 +133,7 @@ always @(*) begin
         CtrlALUOp = 5'd3;//DIV from ALUOps
     end else if((op==SPECIAL)&&(funct==DIVU))begin
         CtrlALUOp = 5'd23;//DIVU from ALUOps
-    end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SBH) || (op==SW))begin
+    end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
         CtrlALUOp = 5'd0;//ADD from ALUOps
     end else if(op==LUI)begin
         CtrlALUOp = 5'd7;//SLL from ALUOps
@@ -189,9 +189,8 @@ always @(*) begin
     end else begin CtrlALUSrc = 1'bx;end
        
     //CtrlRegWrite logic
-    if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))))begin
+    if     ((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
         CtrlRegWrite = 1;//The Registers are Write Enabled
     end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
-     ((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))
 end
 endmodule
diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index ee7544e..b87312c 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -49,7 +49,7 @@ module mips_cpu_memory(
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read
-                data_memory[data_address] <= data_writedata;            
+                data_memory[data_address>>2] <= data_writedata;            
             end
         end
     end

From 1bf7b5d40eeb9cb249ec17b145f7931d62711343 Mon Sep 17 00:00:00 2001
From: Ibrahim <ibzmo28@gmail.com>
Date: Thu, 10 Dec 2020 19:39:04 +0000
Subject: [PATCH 10/15] All instructions except load finished - some test cases
 may need changing upon review

---
 inputs/div.txt              |   4 +
 inputs/divu.txt             |   4 +
 inputs/ibrahimreference.txt | 207 ++++++++++++++++++++++++++++++++++++
 inputs/mfhi.txt             |   4 +
 inputs/mflo.txt             |   5 +
 inputs/mthi.txt             |   3 +
 inputs/mtlo.txt             |   3 +
 inputs/mult.txt             |   5 +
 inputs/multcurrent.txt      |   4 +
 inputs/multu.txt            |   5 +
 inputs/multucurrent.txt     |   4 +
 inputs/or.txt               |   4 +
 inputs/ori.txt              |   6 --
 inputs/reference.txt        |  20 ++--
 inputs/sb.txt               |   4 +
 inputs/sh.txt               |   0
 16 files changed, 270 insertions(+), 12 deletions(-)
 create mode 100644 inputs/div.txt
 create mode 100644 inputs/divu.txt
 create mode 100644 inputs/mfhi.txt
 create mode 100644 inputs/mflo.txt
 create mode 100644 inputs/mthi.txt
 create mode 100644 inputs/mtlo.txt
 create mode 100644 inputs/mult.txt
 create mode 100644 inputs/multcurrent.txt
 create mode 100644 inputs/multu.txt
 create mode 100644 inputs/multucurrent.txt
 create mode 100644 inputs/or.txt
 create mode 100644 inputs/sb.txt
 create mode 100644 inputs/sh.txt

diff --git a/inputs/div.txt b/inputs/div.txt
new file mode 100644
index 0000000..6dcc0f5
--- /dev/null
+++ b/inputs/div.txt
@@ -0,0 +1,4 @@
+34040004
+34050003
+0085001A
+00000008
\ No newline at end of file
diff --git a/inputs/divu.txt b/inputs/divu.txt
new file mode 100644
index 0000000..039725b
--- /dev/null
+++ b/inputs/divu.txt
@@ -0,0 +1,4 @@
+34040004
+34050003
+0085001B
+00000008
\ No newline at end of file
diff --git a/inputs/ibrahimreference.txt b/inputs/ibrahimreference.txt
index 64df695..ddcf491 100644
--- a/inputs/ibrahimreference.txt
+++ b/inputs/ibrahimreference.txt
@@ -271,4 +271,211 @@ register 0 = 16
 
 34040003
 00041080
+00000008
+
+======== SB	Store byte =======
+
+ori $4, $0, 1029
+ori $5, $0, 1
+sb $4, 1($5)
+jr $0
+
+register 0 = 5
+
+34040405
+34050001
+a0a40001
+00000008
+
+ ======== ORI	Bitwise or immediate ===
+
+ori $4,$0,3
+jr $0
+
+register a0 = 3
+
+34040003
+00000008
+
+======== OR	Bitwise or  ===
+
+int main(){
+    int a =5;
+    int b= 3;
+
+    int c = 5 | 3;
+
+    return 0;
+}
+
+
+ori $4, $0, 5
+ori $5, $0, 3
+or $2, $4, $5
+jr $0
+
+
+34040005
+34050003
+00851025
+00000008
+
+register 0 = 7
+
+======= MULT	Multiply =====
+
+ori $4, $0, 4
+ori $5, $0, 3
+mult $4, $5
+jr $0
+
+$LO = 12
+
+34040004
+34050003
+00850018
+00000008
+
+
+======= MULT Multiply =====
+
+ori $4, $0, 4
+ori $5, $0, 3
+mult $4, $5
+mflo $2
+jr $0
+
+register v0 = 12
+
+34040004
+34050003
+00850018
+00001012
+00000008
+
+======= MULTU	Multiply unsigned =====
+
+ori $4, $0, 4
+ori $5, $0, 3
+multu $4, $5
+jr $0
+
+
+$LO = 12
+
+34040004
+34050003
+00850019
+00000008
+
+
+======= MULTU	Multiply unsigned =====
+
+ori $4, $0, 4
+ori $5, $0, 3
+multu $4, $5
+mflo $2
+jr $0
+
+
+$2 = 12
+
+34040004
+34050003
+00850019
+00001012
+00000008
+
+======= MFLO Move from lo ======
+
+ori $4, $0, 4
+ori $5, $0, 3
+multu $4, $5
+mflo $2
+jr $0
+
+
+$2 = 12
+
+34040004
+34050003
+00850019
+00001012
+00000008
+
+=========== MFHI Move from Hi ==========
+
+ori $4, $0, 3
+mthi $4
+mfhi $2
+jr $0
+
+register v0 = 3
+
+34040003
+00800011
+00001010
+00000008
+
+======== MTHI	Move to HI ====
+
+ori $4, $0, 5
+mthi $4
+jr $0
+
+
+$HI = 5
+
+34040005
+00800011
+00000008
+
+======= MTLO	Move to LO ===
+
+ori $4, $0, 5
+mtlo $4
+jr $0
+
+
+$HI = 5
+
+34040005
+00800013
+00000008
+
+==================== SH	Store half-word =======
+
+/////////
+
+
+======== DIV Divide  ======
+
+
+ori $4, $0, 4
+ori $5, $0, 3
+div $4, $5
+jr $0
+
+
+$LO = 1
+$HI = 1
+
+34040004
+34050003
+0085001A
+00000008
+
+========= DIVU Divide unsigned =====
+
+ori $4, $0, 4
+ori $5, $0, 3
+divu $4, $5
+jr $0
+
+$LO = 1
+$HI = 1
+
+34040004
+34050003
+0085001B
 00000008
\ No newline at end of file
diff --git a/inputs/mfhi.txt b/inputs/mfhi.txt
new file mode 100644
index 0000000..fd75215
--- /dev/null
+++ b/inputs/mfhi.txt
@@ -0,0 +1,4 @@
+34040003
+00800011
+00001010
+00000008
\ No newline at end of file
diff --git a/inputs/mflo.txt b/inputs/mflo.txt
new file mode 100644
index 0000000..db18ff6
--- /dev/null
+++ b/inputs/mflo.txt
@@ -0,0 +1,5 @@
+34040004
+34050003
+00850019
+00001012
+00000008
diff --git a/inputs/mthi.txt b/inputs/mthi.txt
new file mode 100644
index 0000000..a8cc125
--- /dev/null
+++ b/inputs/mthi.txt
@@ -0,0 +1,3 @@
+34040005
+00800011
+00000008
\ No newline at end of file
diff --git a/inputs/mtlo.txt b/inputs/mtlo.txt
new file mode 100644
index 0000000..dc818bc
--- /dev/null
+++ b/inputs/mtlo.txt
@@ -0,0 +1,3 @@
+34040005
+00800013
+00000008
\ No newline at end of file
diff --git a/inputs/mult.txt b/inputs/mult.txt
new file mode 100644
index 0000000..86f65a6
--- /dev/null
+++ b/inputs/mult.txt
@@ -0,0 +1,5 @@
+34040004
+34050003
+00850018
+00001012
+00000008
\ No newline at end of file
diff --git a/inputs/multcurrent.txt b/inputs/multcurrent.txt
new file mode 100644
index 0000000..38f4bf0
--- /dev/null
+++ b/inputs/multcurrent.txt
@@ -0,0 +1,4 @@
+34040004
+34050003
+00850018
+00000008
\ No newline at end of file
diff --git a/inputs/multu.txt b/inputs/multu.txt
new file mode 100644
index 0000000..bae2062
--- /dev/null
+++ b/inputs/multu.txt
@@ -0,0 +1,5 @@
+34040004
+34050003
+00850019
+00001012
+00000008
\ No newline at end of file
diff --git a/inputs/multucurrent.txt b/inputs/multucurrent.txt
new file mode 100644
index 0000000..7f898e1
--- /dev/null
+++ b/inputs/multucurrent.txt
@@ -0,0 +1,4 @@
+34040004
+34050003
+00850019
+00000008
\ No newline at end of file
diff --git a/inputs/or.txt b/inputs/or.txt
new file mode 100644
index 0000000..25df299
--- /dev/null
+++ b/inputs/or.txt
@@ -0,0 +1,4 @@
+34040005
+34050003
+00851025
+00000008
\ No newline at end of file
diff --git a/inputs/ori.txt b/inputs/ori.txt
index 996347b..902d413 100644
--- a/inputs/ori.txt
+++ b/inputs/ori.txt
@@ -1,8 +1,2 @@
 34040003
 00000008
-00000000
-00000000
-00000000
-00000000
-00000000
-00000000
\ No newline at end of file
diff --git a/inputs/reference.txt b/inputs/reference.txt
index c947c50..10792b3 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -330,13 +330,21 @@ LW	Load word
 LWL	Load word left
 LWR	Load word right
 
+// DIVU Divide unsigned
+
+// DIV Divide
+
+//MFHI Move from Hi 
+
+//MFLO Move from lo 
+
 //MTHI	Move to HI
 
 //MTLO	Move to LO
 
-//MULT	Multiply
+//MULT	Multiply**
 
-//MULTU	Multiply unsigned
+//MULTU	Multiply unsigned**
 
 //OR	Bitwise or
 
@@ -344,11 +352,11 @@ LWR	Load word right
 
 //SB	Store byte
 
-//SH	Store half-word
+//SH	Store half-word**
 
 //SLL	Shift left logical
 
-//SLLV	Shift left logical variable
+//SLLV	Shift left logical variable **
 
 //SLT	Set on less than (signed)
 
@@ -360,11 +368,11 @@ LWR	Load word right
 
 //SRA	Shift right arithmetic
 
-//SRAV	Shift right arithmetic
+//SRAV	Shift right arithmetic**
 
 //SRL	Shift right logical
 
-//SRLV	Shift right logical variable
+//SRLV	Shift right logical variable**
 
 //SUBU	Subtract unsigned
 
diff --git a/inputs/sb.txt b/inputs/sb.txt
new file mode 100644
index 0000000..01cfb59
--- /dev/null
+++ b/inputs/sb.txt
@@ -0,0 +1,4 @@
+34040405
+34050001
+a0a40001
+00000008
\ No newline at end of file
diff --git a/inputs/sh.txt b/inputs/sh.txt
new file mode 100644
index 0000000..e69de29

From 7ffd8fb40026958c0f8b2171b224aa13c2ed701a Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@ic.ac.uk>
Date: Fri, 11 Dec 2020 15:17:43 +0900
Subject: [PATCH 11/15] Add testcases and ref outputs for addiu, and, andi

---
 inputs/addiu.ref.txt  | 1 +
 inputs/addiu.txt      | 3 +++
 inputs/and.ref.txt    | 1 +
 inputs/and.txt        | 4 ++++
 inputs/andi.ref.txt   | 1 +
 inputs/andi.txt       | 5 +++++
 rtl/mips_cpu_memory.v | 2 +-
 7 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 inputs/addiu.ref.txt
 create mode 100644 inputs/addiu.txt
 create mode 100644 inputs/and.ref.txt
 create mode 100644 inputs/and.txt
 create mode 100644 inputs/andi.ref.txt
 create mode 100644 inputs/andi.txt

diff --git a/inputs/addiu.ref.txt b/inputs/addiu.ref.txt
new file mode 100644
index 0000000..8580e7b
--- /dev/null
+++ b/inputs/addiu.ref.txt
@@ -0,0 +1 @@
+30
\ No newline at end of file
diff --git a/inputs/addiu.txt b/inputs/addiu.txt
new file mode 100644
index 0000000..62290ae
--- /dev/null
+++ b/inputs/addiu.txt
@@ -0,0 +1,3 @@
+3404000a
+24820014
+00000008
\ No newline at end of file
diff --git a/inputs/and.ref.txt b/inputs/and.ref.txt
new file mode 100644
index 0000000..9a03714
--- /dev/null
+++ b/inputs/and.ref.txt
@@ -0,0 +1 @@
+10
\ No newline at end of file
diff --git a/inputs/and.txt b/inputs/and.txt
new file mode 100644
index 0000000..24529d7
--- /dev/null
+++ b/inputs/and.txt
@@ -0,0 +1,4 @@
+3404000A
+3405000F
+00851024
+00000008
\ No newline at end of file
diff --git a/inputs/andi.ref.txt b/inputs/andi.ref.txt
new file mode 100644
index 0000000..7813681
--- /dev/null
+++ b/inputs/andi.ref.txt
@@ -0,0 +1 @@
+5
\ No newline at end of file
diff --git a/inputs/andi.txt b/inputs/andi.txt
new file mode 100644
index 0000000..74b3184
--- /dev/null
+++ b/inputs/andi.txt
@@ -0,0 +1,5 @@
+34040005
+3082000f
+00000008
+00000000
+00000000
\ No newline at end of file
diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v
index b87312c..13b4015 100644
--- a/rtl/mips_cpu_memory.v
+++ b/rtl/mips_cpu_memory.v
@@ -45,7 +45,7 @@ module mips_cpu_memory(
 
     //Synchronous write path
     always_ff @(posedge clk) begin
-        $display("Instruction Read: %h", instr_readdata);
+        //$display("Instruction Read: %h", instr_readdata);
         //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (!data_read & data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read

From 47e0f42f92ac3688286569c11c68cded554994b2 Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Fri, 11 Dec 2020 15:54:23 +0800
Subject: [PATCH 12/15] added load instructions

---
 inputs/reference.txt | 189 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 178 insertions(+), 11 deletions(-)

diff --git a/inputs/reference.txt b/inputs/reference.txt
index 10792b3..ed39c2c 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -34,15 +34,27 @@ LUI $4,0xAAAA
 AND  $2,$4,$5
 JR $0
 
+3405cccc
+3c05cccc
+3404aaaa
+3c04aaaa
+00851024
+00000008
+
 register_v0 = 0x88888888
 
 ==ANDI Bitwise and immediate==
 
 ORI $4,$0,0xAAAA
 LUI $4,0xAAAA  
-ANDI  $2,$4,0xCCCC
+ANDI $2,$4,0xCCCC
 JR $0
 
+3404aaaa
+3c04aaaa
+3082cccc
+00000008
+
 register_v0 = 0x00008888
 
 ==BEQ	Branch on equal==
@@ -223,18 +235,34 @@ MFLO $5
 ADDU $2,$4,$5
 JR $0
 
+34040003
+34050009
+00A4001A
+00002010
+00002812
+00851021
+00000008
+
 register_v0 = 3
 
 ==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
 
 LUI $4,0x8000 
 ORI $5,$0,2
-DIV  $4,$5
+DIVU  $4,$5
 MFHI $4
 MFLO $5
 ADDU $2,$4,$5
 JR $0
 
+34048000
+34050002
+0085001B
+00002010
+00002812
+00851021
+00000008
+
 register_v0 = 0x40000000
 
 ==J	Jump==
@@ -277,7 +305,6 @@ JR $4
 34020001
 00800008
 
-
 register_v0 = 2
 
 ==JAL	Jump and link==
@@ -321,14 +348,154 @@ JR $0
 
 register_v0 = 1
 
-LB	Load byte
-LBU	Load byte unsigned
-LH	Load half-word
-LHU	Load half-word unsigned
-LUI	Load upper immediate
-LW	Load word
-LWL	Load word left
-LWR	Load word right
+==LB	Load byte==
+
+ORI $4,$0,0x1003
+LB  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+80820003
+00000008
+
+-Memory Hex
+
+00000000
+008A0000
+
+register_v0 = 0xFFFFFF8A
+
+==LBU	Load byte unsigned==
+
+ORI $4,$0,0x1003
+LBU  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+90820003
+00000008
+
+-Memory Hex
+
+00000000
+008A0000
+
+register_v0 = 0x0000008A
+
+==LH	Load half-word==
+
+ORI $4,$0,0x1003
+LH  $2,4($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+84820004
+00000008
+
+-Memory Hex
+
+00000000
+00008123
+
+register_v0 = 0xFFFF8123
+
+==LHU	Load half-word unsigned==
+
+ORI $4,$0,0x1003
+LHU $2,4($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+94820004
+00000008
+
+-Memory Hex
+
+00000000
+00008123
+
+register_v0 = 0x00008123
+
+==LUI	Load upper immediate==
+
+ORI $2,$0,0x5678
+LUI $2,0x1234
+JR $0
+
+34045678
+3C021234
+00000008
+
+register_v0 = 0x12345678
+
+==LW	Load word==
+
+ORI $4,$0,0x1002
+LW  $2, 2($4)
+JR $0
+
+-Instruction Hex
+
+34041002
+8C820002
+00000008
+
+-Memory Hex
+
+00000000
+12345678
+
+register_v0 = 0x12345678
+
+==LWL	Load word left==
+
+ORI $4,$0,0x1003
+ORI $2,$0,0x5678
+LWL  $2,3($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+34025678
+88820003
+00000008
+
+-Memory Hex
+
+00000000
+AAAA1234
+
+register_v0 = 0x12345678
+
+==LWR	Load word right==
+
+ORI $4,$0,0x1003
+LUI $2,0x1234
+LWR $2,2($4)
+JR $0
+
+-Instruction Hex
+
+34041003
+3C021234
+98820002
+00000008
+
+-Memory Hex
+
+00000000
+5678AAAA
+
+register_v0 = 0x12345678
 
 // DIVU Divide unsigned
 

From 69cd711cfcc54e8d1baa2ff2947e32cfbc2e99db Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Sat, 12 Dec 2020 23:39:00 +0800
Subject: [PATCH 13/15] Added load instruction txt and data.txt

---
 inputs/lb.data.txt   |  4 ++++
 inputs/lb.txt        |  3 +++
 inputs/lbu.data.txt  |  4 ++++
 inputs/lbu.txt       |  3 +++
 inputs/lh.data.txt   |  4 ++++
 inputs/lh.txt        |  3 +++
 inputs/lhu.data.txt  |  4 ++++
 inputs/lhu.txt       |  3 +++
 inputs/lui.txt       |  3 +++
 inputs/lw.data.txt   |  4 ++++
 inputs/lw.txt        |  3 +++
 inputs/lwl.data.txt  |  4 ++++
 inputs/lwl.txt       |  4 ++++
 inputs/lwr.data.txt  |  4 ++++
 inputs/lwr.txt       |  4 ++++
 inputs/reference.txt | 14 ++++++++++++++
 16 files changed, 68 insertions(+)
 create mode 100644 inputs/lb.data.txt
 create mode 100644 inputs/lb.txt
 create mode 100644 inputs/lbu.data.txt
 create mode 100644 inputs/lbu.txt
 create mode 100644 inputs/lh.data.txt
 create mode 100644 inputs/lh.txt
 create mode 100644 inputs/lhu.data.txt
 create mode 100644 inputs/lhu.txt
 create mode 100644 inputs/lui.txt
 create mode 100644 inputs/lw.data.txt
 create mode 100644 inputs/lw.txt
 create mode 100644 inputs/lwl.data.txt
 create mode 100644 inputs/lwl.txt
 create mode 100644 inputs/lwr.data.txt
 create mode 100644 inputs/lwr.txt

diff --git a/inputs/lb.data.txt b/inputs/lb.data.txt
new file mode 100644
index 0000000..47c26d6
--- /dev/null
+++ b/inputs/lb.data.txt
@@ -0,0 +1,4 @@
+00000000
+008A0000
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lb.txt b/inputs/lb.txt
new file mode 100644
index 0000000..83898a5
--- /dev/null
+++ b/inputs/lb.txt
@@ -0,0 +1,3 @@
+34041003
+80820003
+00000008
\ No newline at end of file
diff --git a/inputs/lbu.data.txt b/inputs/lbu.data.txt
new file mode 100644
index 0000000..47c26d6
--- /dev/null
+++ b/inputs/lbu.data.txt
@@ -0,0 +1,4 @@
+00000000
+008A0000
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lbu.txt b/inputs/lbu.txt
new file mode 100644
index 0000000..06c0f06
--- /dev/null
+++ b/inputs/lbu.txt
@@ -0,0 +1,3 @@
+34041003
+90820003
+00000008
\ No newline at end of file
diff --git a/inputs/lh.data.txt b/inputs/lh.data.txt
new file mode 100644
index 0000000..f3b4cfd
--- /dev/null
+++ b/inputs/lh.data.txt
@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lh.txt b/inputs/lh.txt
new file mode 100644
index 0000000..3a583e1
--- /dev/null
+++ b/inputs/lh.txt
@@ -0,0 +1,3 @@
+34041003
+84820004
+00000008
\ No newline at end of file
diff --git a/inputs/lhu.data.txt b/inputs/lhu.data.txt
new file mode 100644
index 0000000..f3b4cfd
--- /dev/null
+++ b/inputs/lhu.data.txt
@@ -0,0 +1,4 @@
+00000000
+00008123
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lhu.txt b/inputs/lhu.txt
new file mode 100644
index 0000000..54a3692
--- /dev/null
+++ b/inputs/lhu.txt
@@ -0,0 +1,3 @@
+34041003
+94820004
+00000008
\ No newline at end of file
diff --git a/inputs/lui.txt b/inputs/lui.txt
new file mode 100644
index 0000000..6c9915e
--- /dev/null
+++ b/inputs/lui.txt
@@ -0,0 +1,3 @@
+34045678
+3C021234
+00000008
\ No newline at end of file
diff --git a/inputs/lw.data.txt b/inputs/lw.data.txt
new file mode 100644
index 0000000..50de8d2
--- /dev/null
+++ b/inputs/lw.data.txt
@@ -0,0 +1,4 @@
+00000000
+12345678
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lw.txt b/inputs/lw.txt
new file mode 100644
index 0000000..7c6a2ee
--- /dev/null
+++ b/inputs/lw.txt
@@ -0,0 +1,3 @@
+34041002
+8C820002
+00000008
\ No newline at end of file
diff --git a/inputs/lwl.data.txt b/inputs/lwl.data.txt
new file mode 100644
index 0000000..325d898
--- /dev/null
+++ b/inputs/lwl.data.txt
@@ -0,0 +1,4 @@
+00000000
+AAAA1234
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lwl.txt b/inputs/lwl.txt
new file mode 100644
index 0000000..a62ec0b
--- /dev/null
+++ b/inputs/lwl.txt
@@ -0,0 +1,4 @@
+34041003
+34025678
+88820003
+00000008
\ No newline at end of file
diff --git a/inputs/lwr.data.txt b/inputs/lwr.data.txt
new file mode 100644
index 0000000..ca679b8
--- /dev/null
+++ b/inputs/lwr.data.txt
@@ -0,0 +1,4 @@
+00000000
+5678AAAA
+00000000
+00000000
\ No newline at end of file
diff --git a/inputs/lwr.txt b/inputs/lwr.txt
new file mode 100644
index 0000000..22f33f9
--- /dev/null
+++ b/inputs/lwr.txt
@@ -0,0 +1,4 @@
+34041003
+3C021234
+98820002
+00000008
\ No newline at end of file
diff --git a/inputs/reference.txt b/inputs/reference.txt
index ed39c2c..ff067cb 100644
--- a/inputs/reference.txt
+++ b/inputs/reference.txt
@@ -364,6 +364,8 @@ JR $0
 
 00000000
 008A0000
+00000000
+00000000
 
 register_v0 = 0xFFFFFF8A
 
@@ -383,6 +385,8 @@ JR $0
 
 00000000
 008A0000
+00000000
+00000000
 
 register_v0 = 0x0000008A
 
@@ -402,6 +406,8 @@ JR $0
 
 00000000
 00008123
+00000000
+00000000
 
 register_v0 = 0xFFFF8123
 
@@ -421,6 +427,8 @@ JR $0
 
 00000000
 00008123
+00000000
+00000000
 
 register_v0 = 0x00008123
 
@@ -452,6 +460,8 @@ JR $0
 
 00000000
 12345678
+00000000
+00000000
 
 register_v0 = 0x12345678
 
@@ -473,6 +483,8 @@ JR $0
 
 00000000
 AAAA1234
+00000000
+00000000
 
 register_v0 = 0x12345678
 
@@ -494,6 +506,8 @@ JR $0
 
 00000000
 5678AAAA
+00000000
+00000000
 
 register_v0 = 0x12345678
 

From ab27fcaed379881e4723cf5f762a2128be0d632a Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Sat, 12 Dec 2020 23:46:42 +0800
Subject: [PATCH 14/15] Reference txt now in reference folders

---
 .DS_Store                                   | Bin 0 -> 10244 bytes
 inputs/.DS_Store                            | Bin 0 -> 10244 bytes
 inputs/{ => reference}/ibrahimreference.txt |   0
 inputs/{ => reference}/reference.txt        |   0
 4 files changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 .DS_Store
 create mode 100644 inputs/.DS_Store
 rename inputs/{ => reference}/ibrahimreference.txt (100%)
 rename inputs/{ => reference}/reference.txt (100%)

diff --git a/.DS_Store b/.DS_Store
new file mode 100644
index 0000000000000000000000000000000000000000..d6cace5b3b482de4a8700a09e4a767c40f3a57e6
GIT binary patch
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diff --git a/inputs/.DS_Store b/inputs/.DS_Store
new file mode 100644
index 0000000000000000000000000000000000000000..6dacc4f72b26423abeda22eab0deea7702347e0d
GIT binary patch
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HcmV?d00001

diff --git a/inputs/ibrahimreference.txt b/inputs/reference/ibrahimreference.txt
similarity index 100%
rename from inputs/ibrahimreference.txt
rename to inputs/reference/ibrahimreference.txt
diff --git a/inputs/reference.txt b/inputs/reference/reference.txt
similarity index 100%
rename from inputs/reference.txt
rename to inputs/reference/reference.txt

From 276f7f821673c5e7dbf918cce5336543826f24f7 Mon Sep 17 00:00:00 2001
From: yhp19 <yhp19@imperial.ac.uk>
Date: Sat, 12 Dec 2020 23:59:04 +0800
Subject: [PATCH 15/15] Added ref files for j and load instructions

---
 inputs/j.ref.txt    | 1 +
 inputs/jal.ref.txt  | 1 +
 inputs/jalr.ref.txt | 1 +
 inputs/jr.ref.txt   | 1 +
 inputs/lb.ref.txt   | 1 +
 inputs/lbu.ref.txt  | 1 +
 inputs/lh.ref.txt   | 1 +
 inputs/lhu.ref.txt  | 1 +
 inputs/lui.ref.txt  | 1 +
 inputs/lw.ref.txt   | 1 +
 inputs/lwl.ref.txt  | 1 +
 inputs/lwr.ref.txt  | 1 +
 12 files changed, 12 insertions(+)
 create mode 100644 inputs/j.ref.txt
 create mode 100644 inputs/jal.ref.txt
 create mode 100644 inputs/jalr.ref.txt
 create mode 100644 inputs/jr.ref.txt
 create mode 100644 inputs/lb.ref.txt
 create mode 100644 inputs/lbu.ref.txt
 create mode 100644 inputs/lh.ref.txt
 create mode 100644 inputs/lhu.ref.txt
 create mode 100644 inputs/lui.ref.txt
 create mode 100644 inputs/lw.ref.txt
 create mode 100644 inputs/lwl.ref.txt
 create mode 100644 inputs/lwr.ref.txt

diff --git a/inputs/j.ref.txt b/inputs/j.ref.txt
new file mode 100644
index 0000000..56a6051
--- /dev/null
+++ b/inputs/j.ref.txt
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/inputs/jal.ref.txt b/inputs/jal.ref.txt
new file mode 100644
index 0000000..d8263ee
--- /dev/null
+++ b/inputs/jal.ref.txt
@@ -0,0 +1 @@
+2
\ No newline at end of file
diff --git a/inputs/jalr.ref.txt b/inputs/jalr.ref.txt
new file mode 100644
index 0000000..d8263ee
--- /dev/null
+++ b/inputs/jalr.ref.txt
@@ -0,0 +1 @@
+2
\ No newline at end of file
diff --git a/inputs/jr.ref.txt b/inputs/jr.ref.txt
new file mode 100644
index 0000000..56a6051
--- /dev/null
+++ b/inputs/jr.ref.txt
@@ -0,0 +1 @@
+1
\ No newline at end of file
diff --git a/inputs/lb.ref.txt b/inputs/lb.ref.txt
new file mode 100644
index 0000000..f8ff60d
--- /dev/null
+++ b/inputs/lb.ref.txt
@@ -0,0 +1 @@
+4294967178
\ No newline at end of file
diff --git a/inputs/lbu.ref.txt b/inputs/lbu.ref.txt
new file mode 100644
index 0000000..eafdfb0
--- /dev/null
+++ b/inputs/lbu.ref.txt
@@ -0,0 +1 @@
+138
\ No newline at end of file
diff --git a/inputs/lh.ref.txt b/inputs/lh.ref.txt
new file mode 100644
index 0000000..9e489ac
--- /dev/null
+++ b/inputs/lh.ref.txt
@@ -0,0 +1 @@
+4294934819
\ No newline at end of file
diff --git a/inputs/lhu.ref.txt b/inputs/lhu.ref.txt
new file mode 100644
index 0000000..db277c1
--- /dev/null
+++ b/inputs/lhu.ref.txt
@@ -0,0 +1 @@
+33059
\ No newline at end of file
diff --git a/inputs/lui.ref.txt b/inputs/lui.ref.txt
new file mode 100644
index 0000000..7751570
--- /dev/null
+++ b/inputs/lui.ref.txt
@@ -0,0 +1 @@
+305419896
\ No newline at end of file
diff --git a/inputs/lw.ref.txt b/inputs/lw.ref.txt
new file mode 100644
index 0000000..7751570
--- /dev/null
+++ b/inputs/lw.ref.txt
@@ -0,0 +1 @@
+305419896
\ No newline at end of file
diff --git a/inputs/lwl.ref.txt b/inputs/lwl.ref.txt
new file mode 100644
index 0000000..7751570
--- /dev/null
+++ b/inputs/lwl.ref.txt
@@ -0,0 +1 @@
+305419896
\ No newline at end of file
diff --git a/inputs/lwr.ref.txt b/inputs/lwr.ref.txt
new file mode 100644
index 0000000..7751570
--- /dev/null
+++ b/inputs/lwr.ref.txt
@@ -0,0 +1 @@
+305419896
\ No newline at end of file